WO2008137079A3 - Data processing device with low-power cache access mode - Google Patents

Data processing device with low-power cache access mode Download PDF

Info

Publication number
WO2008137079A3
WO2008137079A3 PCT/US2008/005692 US2008005692W WO2008137079A3 WO 2008137079 A3 WO2008137079 A3 WO 2008137079A3 US 2008005692 W US2008005692 W US 2008005692W WO 2008137079 A3 WO2008137079 A3 WO 2008137079A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
low
mode
voltage
data processing
Prior art date
Application number
PCT/US2008/005692
Other languages
French (fr)
Other versions
WO2008137079A2 (en
Inventor
Alex Branover
Frank P Helms
Maurice Steinman
Original Assignee
Advanced Micro Devices Inc
Alex Branover
Frank P Helms
Maurice Steinman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Alex Branover, Frank P Helms, Maurice Steinman filed Critical Advanced Micro Devices Inc
Priority to GB0918043A priority Critical patent/GB2460602B/en
Priority to CN200880014524A priority patent/CN101730872A/en
Priority to JP2010506332A priority patent/JP5427775B2/en
Priority to DE112008001223T priority patent/DE112008001223B4/en
Publication of WO2008137079A2 publication Critical patent/WO2008137079A2/en
Publication of WO2008137079A3 publication Critical patent/WO2008137079A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3243Power saving in microcontroller unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3275Power saving in memory, e.g. RAM, cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3287Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/3296Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions (402). In a low-power mode, a retention voltage is provided to the processor (408). The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode (412).
PCT/US2008/005692 2007-05-02 2008-05-02 Data processing device with low-power cache access mode WO2008137079A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0918043A GB2460602B (en) 2007-05-02 2008-05-02 Data processing device with low-power cache access mode
CN200880014524A CN101730872A (en) 2007-05-02 2008-05-02 Data processing device with low-power cache access mode
JP2010506332A JP5427775B2 (en) 2007-05-02 2008-05-02 Data processing device with low power cache access mode
DE112008001223T DE112008001223B4 (en) 2007-05-02 2008-05-02 Data processing with a low power cache access mode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/743,388 US7941683B2 (en) 2007-05-02 2007-05-02 Data processing device with low-power cache access mode
US11/743,388 2007-05-02

Publications (2)

Publication Number Publication Date
WO2008137079A2 WO2008137079A2 (en) 2008-11-13
WO2008137079A3 true WO2008137079A3 (en) 2009-07-02

Family

ID=39940497

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/005692 WO2008137079A2 (en) 2007-05-02 2008-05-02 Data processing device with low-power cache access mode

Country Status (8)

Country Link
US (1) US7941683B2 (en)
JP (1) JP5427775B2 (en)
KR (1) KR101473907B1 (en)
CN (1) CN101730872A (en)
DE (1) DE112008001223B4 (en)
GB (1) GB2460602B (en)
TW (1) TW200910078A (en)
WO (1) WO2008137079A2 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8156353B2 (en) * 2007-09-17 2012-04-10 Intel Corporation Techniques for communications power management based on system states
US8028181B2 (en) * 2008-09-19 2011-09-27 Intel Corporation Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
US9678878B2 (en) 2008-09-30 2017-06-13 Intel Corporation Disabling cache portions during low voltage operations
US8103830B2 (en) 2008-09-30 2012-01-24 Intel Corporation Disabling cache portions during low voltage operations
US8352819B2 (en) * 2009-04-15 2013-01-08 Arm Limited State retention using a variable retention voltage
US20110112798A1 (en) * 2009-11-06 2011-05-12 Alexander Branover Controlling performance/power by frequency control of the responding node
US20120096290A1 (en) * 2010-10-14 2012-04-19 Keynetik, Inc. Distributed Architecture for Situation Aware Sensory Application
US8639960B2 (en) 2011-05-27 2014-01-28 Arm Limited Verifying state integrity in state retention circuits
US8732499B2 (en) 2011-05-27 2014-05-20 Arm Limited State retention circuit adapted to allow its state integrity to be verified
JP2013008270A (en) * 2011-06-27 2013-01-10 Renesas Electronics Corp Parallel arithmetic unit and microcomputer
US20130124891A1 (en) * 2011-07-15 2013-05-16 Aliphcom Efficient control of power consumption in portable sensing devices
US20130117511A1 (en) * 2011-11-08 2013-05-09 Arm Limited Data processing apparatus and method
US9063734B2 (en) * 2012-09-07 2015-06-23 Atmel Corporation Microcontroller input/output connector state retention in low-power modes
US9317100B2 (en) * 2013-01-10 2016-04-19 Advanced Micro Devices, Inc. Accelerated cache rinse when preparing a power state transition
KR101475931B1 (en) * 2013-05-24 2014-12-23 고려대학교 산학협력단 Cache and method for operating the same
JP6130750B2 (en) * 2013-07-16 2017-05-17 株式会社東芝 Memory control circuit and processor
US9965220B2 (en) 2016-02-05 2018-05-08 Qualcomm Incorporated Forced idling of memory subsystems
US20180024610A1 (en) * 2016-07-22 2018-01-25 Futurewei Technologies, Inc. Apparatus and method for setting a clock speed/voltage of cache memory based on memory request information

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040255176A1 (en) * 2003-06-10 2004-12-16 Varghese George Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014751A (en) * 1997-05-05 2000-01-11 Intel Corporation Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state
JPH11161383A (en) * 1997-09-05 1999-06-18 Texas Instr Inc <Ti> Microprocessor circuit, its system, and method for controlling power consumption of microprocessor in response to on-chip activity
US6118306A (en) * 1998-12-03 2000-09-12 Intel Corporation Changing clock frequency
US6795896B1 (en) * 2000-09-29 2004-09-21 Intel Corporation Methods and apparatuses for reducing leakage power consumption in a processor
US6988211B2 (en) * 2000-12-29 2006-01-17 Intel Corporation System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field
US6920574B2 (en) * 2002-04-29 2005-07-19 Apple Computer, Inc. Conserving power by reducing voltage supplied to an instruction-processing portion of a processor
JP3857661B2 (en) * 2003-03-13 2006-12-13 インターナショナル・ビジネス・マシーンズ・コーポレーション Information processing apparatus, program, and recording medium
KR20060013415A (en) * 2003-05-27 2006-02-09 인터내셔널 비지네스 머신즈 코포레이션 Power saving inhibiting factor identification system, information processing device, power saving inhibiting factor identification method, program, and recording medium
GB2403561A (en) * 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Power control within a coherent multi-processor system
US7664970B2 (en) * 2005-12-30 2010-02-16 Intel Corporation Method and apparatus for a zero voltage processor sleep state
US7337335B2 (en) * 2004-12-21 2008-02-26 Packet Digital Method and apparatus for on-demand power management
JP2006318380A (en) * 2005-05-16 2006-11-24 Handotai Rikougaku Kenkyu Center:Kk Circuit system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040255176A1 (en) * 2003-06-10 2004-12-16 Varghese George Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Also Published As

Publication number Publication date
TW200910078A (en) 2009-03-01
GB2460602A (en) 2009-12-09
WO2008137079A2 (en) 2008-11-13
KR101473907B1 (en) 2014-12-17
CN101730872A (en) 2010-06-09
US20080276236A1 (en) 2008-11-06
GB2460602B (en) 2011-09-21
US7941683B2 (en) 2011-05-10
DE112008001223B4 (en) 2013-02-07
JP5427775B2 (en) 2014-02-26
GB0918043D0 (en) 2009-12-02
JP2010526374A (en) 2010-07-29
DE112008001223T5 (en) 2010-03-11
KR20100017583A (en) 2010-02-16

Similar Documents

Publication Publication Date Title
WO2008137079A3 (en) Data processing device with low-power cache access mode
WO2007140404A3 (en) Device having multiple graphics subsystems and reduced power consumption mode, software and methods
WO2008143980A3 (en) Dynamic processor power management device and method thereof
WO2004063916A3 (en) Memory controller considering processor power states
WO2009004757A1 (en) Data processing device, data processing method, data processing program, recording medium, and integrated circuit
WO2009014931A3 (en) Technique for preserving cached information during a low power mode
EP2109028A3 (en) Operations management methods and devices in information processing systems
WO2007024435A3 (en) Dynamic memory sizing for power reduction
EP1603037A3 (en) Processing information received at an auxiliary computing device
WO2006060237A3 (en) Prevention of data loss due to power failure
GB2450448A (en) Method and apparatus for using dynamic workload characteristics to control CPU frequency and voltage scaling
WO2007059085A3 (en) Small and power-efficient cache that can provide data for background dma devices while the processor is in a low-power state
SG137739A1 (en) System with high power and low power processors and thread transfer
WO2013090384A3 (en) Method for soc performance and power optimization
WO2007078628A3 (en) Method and apparatus for providing for detecting processor state transitions
WO2006037119A3 (en) Method and apparatus for varying energy per instruction according to the amount of available parallelism
TW200622683A (en) Task-oriented processing as an auxiliary to primary computing environments
MY146970A (en) Adaptive power management
WO2011046788A3 (en) Memory object relocation for power savings
WO2008118805A3 (en) Processor with adaptive multi-shader
TW200707170A (en) Power management of multiple processors
WO2008033895A3 (en) Method and device for performing user-defined clipping in object space
WO2006125219A3 (en) Caching instructions for a multiple-state processor
TW200643955A (en) Semiconductor memory device and information processing system
WO2006094196A3 (en) Method and apparatus for power reduction in an heterogeneously- multi-pipelined processor

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880014524.9

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 0918043

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20080502

WWE Wipo information: entry into national phase

Ref document number: 0918043.1

Country of ref document: GB

WWE Wipo information: entry into national phase

Ref document number: 2010506332

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1120080012237

Country of ref document: DE

ENP Entry into the national phase

Ref document number: 20097025205

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08767522

Country of ref document: EP

Kind code of ref document: A2

RET De translation (de og part 6b)

Ref document number: 112008001223

Country of ref document: DE

Date of ref document: 20100311

Kind code of ref document: P

122 Ep: pct application non-entry in european phase

Ref document number: 08767522

Country of ref document: EP

Kind code of ref document: A2