WO2009016437A1 - Method of manufacturing a semiconductor device and semiconductor device obtainable therewith - Google Patents
Method of manufacturing a semiconductor device and semiconductor device obtainable therewith Download PDFInfo
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- WO2009016437A1 WO2009016437A1 PCT/IB2007/054859 IB2007054859W WO2009016437A1 WO 2009016437 A1 WO2009016437 A1 WO 2009016437A1 IB 2007054859 W IB2007054859 W IB 2007054859W WO 2009016437 A1 WO2009016437 A1 WO 2009016437A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Definitions
- This invention relates to a method of manufacturing a semiconductor device and to a semiconductor device.
- patent application publication US 2005/0185446 describes a method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices.
- This prior art document discloses a method in which an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the memory cell array and peripheral circuitry areas which contain logic circuitry.
- a thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry.
- This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.
- Figures 1A-J schematically show cross-sectional views of an example of an embodiment of a semiconductor device in different stages of a method of manufacturing non-volatile memory, logic devices and/or high-voltage devices.
- Figures 2A-E schematically show cross-sectional views of an example of an embodiment of a semiconductor device in different stages of a first example of an embodiment of a method according to the invention.
- Figures 3A-B schematically show cross-sectional views of an example of an embodiment of a semiconductor device in different stages of a second example of an embodiment of a method according to the invention.
- Figure 4 schematically shows a cross-sectional view of an example of an embodiment of a semiconductor device in a stage of a third example of an embodiment of a method according to the invention.
- nonvolatile memory for example flash memory or Electrically Erasable Programmable Read Only Memory (EEPROM)
- EEPROM Electrically Erasable Programmable Read Only Memory
- the formation of the non-volatile memory on a substrate may include forming a floating gate structure 14 and a control gate structure 15 in a stacked configuration with the floating gate structure.
- the method may further include forming logic devices 30 on the substrate.
- the formation of the logic devices 30 may include forming a logic gate structure.
- High voltage devices 20 may also be formed, and for example a high voltage gate structure may be formed. Referring to FIG.
- respective areas 1-3 for non-volatile memory 10, high-voltage devices 20, and logic devices 30 may be defined.
- the areas 1-3 may for instance be on different regions a wafer, however the areas 1-3 may also be in the same areas of a wafer.
- the non-volatile memory 10 and/or the high-voltage devices 20 and/or the logic devices 30 may be manufactured more or less simultaneously.
- steps of the manufacturing of the non-volatile memory 10 may be performed simultaneously with steps of the manufacturing of or the logic devices 30 and/or the high-voltage devices 20.
- one or more active regions 1 12 may have been formed, for example in the substrate 4, which is to form the channel of a floating gate field effect transistor and/or part of a logic device and/or high voltage devices, for example by providing the substrate with a suitable doping profile.
- a floating gate structure may be formed on top of the part that will form the channel.
- an oxide layer may be formed, such as a tunnel oxide layer 113, above the active region 112 in the memory area 1.
- gate material may be deposited, such as a second polysilicon layer 1 14.
- a first polysilicon layer 110 or other suitable gate material layer may have been deposited.
- the first polysilicon layer 110 is formed into a gate structure 31 e.g. of the logic devices 30, on top of the active regions in the area 1 of the nonvolatile memory 10.
- the first polysilicon layer 1 10 may for instance be a non patterned layer of uniform thickness that has been deposited in the memory area 1 , the high voltage area 2 and the logic area 3.
- the first polysilicon layer 110 may for example have a thickness of about 0.03 to 0.15 ⁇ m.
- the deposition of the first polysilicon layer 110 may have been preceded by the formation of a gate oxide layer 100 in areas 1-3.
- the thickness of the grown gate oxide layer 100 may for example differ over the surface of the substrate 4 and for example, be a thin gate oxide of 65 A
- Angstrom in the memory area 1 and the high voltage area 2 and have a different thickness in the logic area 3 for different types of logic devices, e.g 25 A and 65 A respectively.
- the first polysilicon layer 110 may be removed in the memory area 1 and be preserved in the other areas 2,3.
- the first polysilicon layer 110 may be etched, for example by providing a protective layer 115 on top of a first polysilicon layer 110 in the areas where the first polysilicon layer 110 is to be preserved, such as the logic area 3 and/or the high-voltage area 2 and exposing the first polysilicon layer 110 to an etching medium in area(s) where the first polysilicon layer 110 is to be removed, such as above an active region 112.
- the gate oxide layer 100 may in the exposed areas, e.g in the memory area 1 , act as an etch stop layer which protects the active region 112 against etching..
- the protective layer 1 15 may for example be a photo-resist layer which is deposited, for example by spinning or other suitable technique, on the substrate 4 and first poly silicon layer 1 10 and patterned using photolithography or other techniques such that the resist is removed above the parts that are to be removed.
- the protective layer 115 may then be removed in a stripping process using a suitable stripping medium, for example by resolving the layer in a suitable solvent or dry resist stripping medium.
- a top surface of the substrate 4 and/or the first polysilicon layer 110 may be oxidized to form the tunnel oxide layer 113 which will act as the gate oxide for the transistors in the memory area 1 .
- the oxide layer may for example have a thickness of less than 10 nm, such as 8.5 nm for example.
- the top surface of substrate 4 may be oxidised after removal of the first polysilicon layer 110.
- the top surface of the first polysilicon layer 110 may also be oxidised at the same time to form a oxide layer in those areas 2,3.
- the second polysilicon layer 114 may be deposited after formation of the oxide layer 1 13.
- the second polysilicon layer 114 may for instance be a non patterned layer of uniform thickness, for example of about 0.03 to 0.15 ⁇ m, that is been deposited in the memory area 1 , the high voltage area 2 and the logic area 3.
- the second polysilicon layer 114 may be deposited on top of the oxide layer 113.
- a stack of the substrate 4 oxide layer 1 13 and the second polysilicon layer 114 is formed.
- the gate oxide layer 100, the first polysilicon layer 1 10, the oxide layer 113 and the second polysilicon layer 114 is formed.
- the second polysilicon layer 1 14 may be patterned to separate for example the floating gates of different non-volatile memory devices from each other. As shown in FIG.
- a patterned resist layer 116 (or other protective layer) may be provided on top of the second polysilicon layer 114, to preserve the second polysilicon layer 114 where desired, such as at the location of the floating gate structures in the memory area 1 and the second polysilicon layer 114 may be - A - removed at the locations not covered by the resist layer 116.
- an Anti reflective coating (ARC) layer Prior to the photo resist layer 116 an Anti reflective coating (ARC) layer may be deposited prior to the photo resist layer 116.
- ARC Anti reflective coating
- the second polysilicon layer 114 may be etched in an area of a shallow-trench isolation (STI) 117 until the oxide of the STI 117 is reached.
- the second polysilicon layer 1 14 may be exposed to a suitable etching medium.
- the second polysilicon layer 114 may for instance be etched until the top surface of the oxide layer 113 is exposed.
- the oxide layer 113 acts as an etch stop layer in order to protect the fist polysilicon layer 110 from etching.
- the layer 116 may then be removed using a suitable stripping medium, for example by resolving the layer in a suitable solvent or dry resist stripping medium.
- an isolating layer may be formed on top of the floating gate electric layer (which in this example is formed by the second polysilicon layer 114), which will separate the floating gate from the control gate in the memory area 1.
- the floating gate electric layer which in this example is formed by the second polysilicon layer 114
- a stack of Siliconoxide/Siliconnitride/Siliconoxide layers (e.g. SiO2/Si3N4/SiO2), commonly referred to as an Oxide/Nitride/Oxide or ONO layer 118, may be provided where desired, such as in the memory area 1.
- the ONO layer 118 may for example, be of about 16 nm thickness with e.g.
- the ONO layer 118 may for example be deposited in all the areas 1-3 and be etched away where desired such as in the high-voltage area 2.
- a resist layer 119 or other protective layer may be provided, to preserve the ONO layer 1 18 where desired and the parts not covered by the resist layer 119 may be exposed to an etching medium.
- the resist layer 119 is used in at a step that removes the ONO layer 118 and the first poly silicon layer 110 in the High voltage area 2 in order to grow a High voltage oxide.
- a high voltage oxide layer 120 e.g.
- the high voltage oxide layer 120 which may for instance be formed into a high voltage gate dielectric which separates the channel of high-voltage FETs from the gate thereof.
- the high voltage oxide layer 120 may for example be provided after removal in the high-voltage area 2 of the ONO layer 1 18, the oxide layer 113 and the first polysilicon layer 1 10, for example by etching.
- the oxide layer 100 will act as an etch stop layer.
- the resist layer 119 may then be removed, for example using a suitable stripping medium.
- a control gate structure may be provided in a stacked configuration with the floating gate structure.
- a gate material layer may be provided in the parts of the memory area 1 where the control gate structure is to be provided.
- a gate material layer may be provided in the parts of the memory area 1 where the control gate structure is to be provided.
- a third polysilicon layer 121 or other suitable gate material layer may be deposited.
- the third polysilicon layer 121 may for instance have a thickness of 0.03 to 0.15 ⁇ m.
- the third polysilicon layer 121 may be deposited in other areas as well, for example in the high voltage area 2 and the logic area 3.
- the polysilicon layer 121 may be patterned in the memory area 1.
- an amorphous carbon layer 122 and a DARC (Dielectric Anti Reflective Coating) or Antireflective capping layer, such as a Tetra-ethyl-ortho-silicate (TEOS) hard mask layer 123 may be deposited on top of the third polysilicon layer 121 .
- the amorphous carbon layer 122 may for instance have a thickness of 300 nm.
- the carbon layer 122 may for instance be deposited by chemical vapor deposition (CVD) of a gas mixture comprising a carbon source.
- the TEOS layer 123 may for instance have a thickness of 20 nm.
- the TEOS layer 123 may be covered with a layer of resist 124.
- the layer of resist 123 may be patterned in desired areas, such as in the memory area 1 in order to expose the TEOS layer 122, the amorphous carbon layer 122, the third polysilicon layer 121 , the ONO layer 118 and the second polysilicon layer 114 at those locations to an etching medium. Thereby, for instance, separations between different control gates can be created. As shown in FIG. 1 F, the amorphous carbon layer 122 and the TEOS layer 123 may thereafter be removed, for instance using a suitable stripping fluid or using a dry stripping process.
- the third polysilicon layer 121 may be removed in desired areas.
- the third polysilicon layer 121 may be removed entirely, whereas in the high voltage area 2 or the memory area 1 the third polysilicon layer 121 may be removed locally, in order to pattern a structure.
- a high voltage gate structure may be patterned in the third polysilicon layer 121
- in the memory area 1 passages through the polysilicon layer 121 in order to provide contacts to the second polysilicon layer 1 14 which forms the floating gate material in this example
- the third polysilicon layer 121 which forms the control gate material in this example
- a resist layer 125 may for example be provided on the third polysilicon layer 121 and be patterned, such that the third polysilicon layer 121 is exposed in the areas where the third polysilicon layer 121 is to be removed. As shown in FIG. 1 H, for instance in the parts of the memory area 1 where the polysilicon layer 121 is exposed, the polysilicon layer 121 may be etched until the bottom oxide 126 of the ONO layer 118 is exposed. In the high voltage area 2, for instance, the third polysilicon layer 121 may be etched in the parts where it is exposed until the high voltage oxide layer 120 is exposed, to form high voltage gate structures. In the logic area 3, the polysilicon layer 121 may be etched until the bottom oxide 126 of the ONO layer 118 is exposed.
- a resist layer 128 or other protective layer may be provided and patterned in the logic area 3 in order to create gate structures for the logic devices.
- the resist layer 128 may for example be deposited on top of an anti reflective coating (ARC) layer 127A and/or a hard mask layer 127B.
- the exposed parts, that is those not covered by the resist layer 128, may for example be etched.
- the exposed parts of the logic area 3 are etched until the gate oxide layer in order to separate different gate structures from each other in the logic area 3.
- the resist layer 128, the anti reflective coating (ARC) layer 127A and/or the hard mask layer 127B may be removed, resulting in the gate structures of the logic devices, as shown in FIG. U.
- the logic gate structure may for instance be formed by depositing one or more gate material layers and patterning the gate material layers into the logic gate structure 31.
- the gate material may, as explained with reference to FIGs. 1A-J, for example include a polysilicon layer 110.
- the gate may alternatively be of another type of gate material and/or include two or more material layers.
- a filling material layer 130 may be deposited over the memory area 1 and the logic area 3 (and if present, over the high voltage area 2). As illustrated in FIG. 2B, the filling material layer 130 may then be partially removed, by reducing the thickness of the filling material layer 130, at least until a top surface 34 of the one or more gate material layers is exposed. Thereby, the non-uniformity of the topography between the memory area 1 and the logic area 3 may be reduced. Accordingly, the risk of damage to the memory devices, for example due to pitting in the peripheral areas P thereof, may be reduced. Furthermore, the filling material can be deposited (and removed) without requiring a complete overhaul of the flow of processing steps.
- the filling material layer 130 may be partially removed using a suitable process which selectively removes the desired part of the filling material layer 130 while leaving the stack and the gate material layers intact.
- the filling material has filled the empty spaces in logic area 3 and the high voltage areas 2.
- the difference in height between those spaces and the top of the stack is reduced.
- the thickness of the filling material is reduced more or less uniformly over the substrate, until the top surface 34 is just exposed.
- the high voltage area 2 and the logic area 3 have a very low topology and are more or less flat.
- the trenches between the stacks in the memory area 1 are filled by the filling material 130 and after the partial removal of the filling layer 130, the difference in height between the trenches and the top of the stacks is reduced as well.
- the filling material layer 130 is deposited on the hard mask layer 127.
- the hard mask layer 127 may have been deposited over the gate material layer, e.g. the first polysilicon layer 110 in the logic area 3 or the third polysilicon layer 121 in the high voltage area 2, and on the control gate structure 15 in the memory area 1.
- the filling material layer 130 may thus cover the stack of the floating gate structure 14 and the control gate structure 15 and cover the gate material layers in the logic area 3.
- the filling material layer 130 may thus be removed above the stack of the floating gate structure 14 and the control gate structure 15 as well as above the gate material layers, while in the memory area 1 , a part of the filling material layer 130 remains in the trenches between the stacks and, in the high voltage area 2 and the logic area 3, the spaces adjacent to the gate material layers remain (partially) filled with the filling material layer 130.
- the remaining thickness of the filling layer in the trenches between stack(s) may exceed the thickness in the spaces next to the gate material layers and for example be smaller than the height of the stacks but larger than the thickness of the gate material layers.
- the filling material may be subjected to further processing.
- a cure may be performed in order to harden the filling material, for example, to increase the resistance to post processing temperatures.
- the top surface 34 may, for example, be the gate material layer (e.g. in this example the first polysilicon layer) 110 itself or, as shown in FIGs. 2 and 4, a layer 127,133 covering the gate material layer 31.
- the layer covering the gate material layer 110 may for example be a hard mask layer 127, for example a TEOS hard mask or an (inorganic) anti-reflective coating (for example a DARC, Dielectric Anti Reflective Coating) layer 133, as is for instance shown in FIG. 4.
- the layer covering the gate material layer 110 may for example have been provided before the filling material layer 130 is applied. After reduction of the filling material layer 130, a logic gate structure 31 may be formed from the gate material layer 110.
- a photo-resist layer 132 may be deposited on the one or more gate material layers such that the top surface 34 is covered.
- the photo-resist layer 132 may be applied over the whole wafer area.
- the photo-resist layer 132 may for example cover the top surface of the memory area 1 , the high voltage area 2 and the logic area 3.
- the photo-resist layer 132 may be patterned in the logic area 3 such that parts of the top surface 34 are exposed, as shown in FIG. 2C .
- an anti-reflective coating layer (ARC) 131 may have been deposited before depositing the photo-resist layer 132.
- an ARC layer such as a bottom anti- reflective coating (Bare) or a dielectric ARC (DARC) layer may be deposited, for example when no ARC has been deposited before the filling material.
- the ARC layer 131 may for instance be deposited on the top surface of a remaining part of the filling material layer 130 and on the exposed top surface 34.
- the ARC layer 131 may be deposited on the top surfaces in the logic area 3 and other parts such as in the memory area 1 and the high voltage area 2.
- the photo-resist layer 132 may be patterned such that parts of the top surface 34 in the logic area 3 are exposed and the gate material layer may at least partially be removed in the areas where the top surface is exposed.
- first layer forming the top surface in this example the ARC layer 131 , and other layers 127 between the top surface 34 and the gate material layer 31 may be removed.
- the BARC layer 131 and the hard mask layer 127 may be removed at the locations where the top surface 34 is exposed
- the filling material layer 130, the ARC layer 131 and the photo-resist layer 132 may be removed.
- filling material layer 130, the ARC layer 131 and the photo-resist layer 132 may be exposed to suitable stripping media such as a dry resist stripping medium or a suitable solvent liquid.
- this may result in the gate material being covered by a hard mask layer 127 in the areas that were covered by the photo-resist layer 132. Parts of the gate material in the logic area 3 not covered by the a mask layer 127 may then be exposed to an etching medium, resulting in the gate material being removed in those exposed parts 137 and separate gate structures may thereby be obtained, as has been explained with reference to FIG. U.
- the mask layer 127 may then be removed. For example by exposing the mask layer to suitable stripping media such as a dry resist stripping medium or a suitable solvent liquid.
- the filling material layer may be any suitable filling material.
- the filling material may for example be made of a photo-resist or a dielectric resin, or any kind of spin on dielectric or polymers.
- photo-resist sensitive to light in the 1-line from a mercury-vapour lamp has been found to be a suitable type of photo-resist.
- a dielectric resin layer 130' may be used as a filling material.
- a suitable dielectric resin has been found to be the dielectric resin traded under the name SiLK by The Dow Chemical Company.
- a layer 134 of for instance amorphous carbon or other hard mask may be deposited.
- a dielectric antireflective coating (DARC) is applied on top of the amorphous carbon layer 134 .
- DARC dielectric antireflective coating
- a photo resist layer 136 may be deposited on top of the DARC layer 135.
- the photo resist layer 136 may be patterned where desired, for instance in the logic area 3 and subsequently in the parts not covered by the photo resist 136, one or more layers may be etched away.
- the DARC layer 135 and/or the amorphous carbon layer 134 and/or the gate material layer may be removed.
- the remaining photo resist 136, DARC 135, amorphous carbon 134 and filling material 130' may then be removed using suitable processing, such as dry resist stripping or using a suitable solvent.
- the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
- SOI silicon-on-insulator
- the protective layers may be patterned using any suitable patterning technique, such as photo-lithography, electron beam lithography or other suitable patterning techniques.
- any reference signs placed between parentheses shall not be construed as limiting the claim.
- the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
- the words 'a' and 'an' shall not be construed as limited to 'only one', but instead are used to mean 'at least one', and do not exclude a plurality.
Abstract
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PCT/IB2007/054859 WO2009016437A1 (en) | 2007-08-01 | 2007-08-01 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
US12/670,502 US8043951B2 (en) | 2007-08-01 | 2007-08-01 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
KR1020107002371A KR101374579B1 (en) | 2007-08-01 | 2007-08-01 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
JP2010518760A JP2010535410A (en) | 2007-08-01 | 2007-08-01 | Semiconductor device manufacturing method and semiconductor device obtained thereby |
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PCT/IB2007/054859 WO2009016437A1 (en) | 2007-08-01 | 2007-08-01 | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
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US9305931B2 (en) * | 2011-05-10 | 2016-04-05 | Jonker, Llc | Zero cost NVM cell using high voltage devices in analog process |
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US9129996B2 (en) | 2013-07-31 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
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US9082650B2 (en) | 2013-08-21 | 2015-07-14 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic structure |
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US9275864B2 (en) | 2013-08-22 | 2016-03-01 | Freescale Semiconductor,Inc. | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates |
US9136129B2 (en) | 2013-09-30 | 2015-09-15 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology |
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US8901632B1 (en) | 2013-09-30 | 2014-12-02 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
US9231077B2 (en) | 2014-03-03 | 2016-01-05 | Freescale Semiconductor, Inc. | Method of making a logic transistor and non-volatile memory (NVM) cell |
US9112056B1 (en) | 2014-03-28 | 2015-08-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9472418B2 (en) | 2014-03-28 | 2016-10-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9257445B2 (en) | 2014-05-30 | 2016-02-09 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
US9343314B2 (en) | 2014-05-30 | 2016-05-17 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
US9379222B2 (en) | 2014-05-30 | 2016-06-28 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell |
CN107425003B (en) | 2016-05-18 | 2020-07-14 | 硅存储技术公司 | Method of manufacturing split gate non-volatile flash memory cell |
US11527543B2 (en) * | 2020-06-30 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Polysilicon removal in word line contact region of memory devices |
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- 2007-08-01 WO PCT/IB2007/054859 patent/WO2009016437A1/en active Application Filing
- 2007-08-01 US US12/670,502 patent/US8043951B2/en not_active Expired - Fee Related
- 2007-08-01 JP JP2010518760A patent/JP2010535410A/en not_active Withdrawn
- 2007-08-01 KR KR1020107002371A patent/KR101374579B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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US8043951B2 (en) | 2011-10-25 |
US20100227467A1 (en) | 2010-09-09 |
KR101374579B1 (en) | 2014-03-17 |
KR20100049573A (en) | 2010-05-12 |
JP2010535410A (en) | 2010-11-18 |
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