WO2009041781A2 - Polysilicon film and method of forming the same, flash memory device and manufacturing method using the same - Google Patents
Polysilicon film and method of forming the same, flash memory device and manufacturing method using the same Download PDFInfo
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- WO2009041781A2 WO2009041781A2 PCT/KR2008/005706 KR2008005706W WO2009041781A2 WO 2009041781 A2 WO2009041781 A2 WO 2009041781A2 KR 2008005706 W KR2008005706 W KR 2008005706W WO 2009041781 A2 WO2009041781 A2 WO 2009041781A2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 105
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 96
- 230000012010 growth Effects 0.000 claims abstract description 20
- 239000007789 gas Substances 0.000 claims description 102
- 125000004429 atom Chemical group 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 14
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 11
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 239000012071 phase Substances 0.000 description 13
- 210000004940 nucleus Anatomy 0.000 description 11
- 238000004581 coalescence Methods 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000002159 nanocrystal Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003698 anagen phase Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 2
- 229910007264 Si2H6 Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 125000005843 halogen group Chemical group 0.000 description 2
- 238000011534 incubation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Definitions
- the present invention relates to a polysilicon film and a method of manufacturing the same, and more particularly, to a polysilicon film having nano-size grains and a method of forming the same, and a flash memory device employing the polysilicon film and a method of manufacturing the flash memory device.
- a flash memory device is a non- volatile memory device that can program and erase data, and read out the programmed data.
- the flash memory device has a cell structure that includes a gate electrode insulated from a semiconductor substrate by a tunnel oxide layer and formed with a dielectric layer interposed between a floating gate and a control gate, and source/drain junction regions disposed at both sides of the gate electrode.
- the flash memory device is programmed and erased performing an operation of injecting charge onto the floating gate and pulling the charge off the floating gate. That is, a positive voltage applied to the control gate is coupled to the floating gate and thus the flash memory device is programed by electrons that are captured into the floating gate through the tunnel oxide layer from the substrate through Fowler-Nordheim (FN) tunneling or hot-carrier injection. On the other hand, in the erase operation, the electrons within the floating gate are moved into the substrate by a negative voltage applied to the control gate.
- FN Fowler-Nordheim
- the floating gate of the flash memory device may include a polysilicon film.
- a design rule decreases, in a flash memory device having a design rule less than 40 nm, it is required to increase the number of grains in a polysilicon film used as a floating gate as well as increasing a tunneling field in order to perform a high-speed program by reducing a threshold voltage.
- the grain size of the polysilicon film should be reduced. As the grain size is reduced, the number of grain boundaries is increased and thus an erasing speed of the flash memory device becomes high. That is, a programming speed and the erasing speed of the flash memory device can be improved by reducing the grain size of the polysilicon film used as the floating gate.
- the polysilicon film is formed through several phases such as an incubation phase, a nucleation and growth phase, a growth dominated phase, and a complete coalescence phase.
- silicon adatom reaches onto a surface of the tunnel oxide layer and a first stable nucleus is generated.
- nucleation and growth phase new nucleuses are consecutively generated while the previously generated nucleuses grow into nanocrystals.
- growth dominated phase the generation of new nucleuses is stopped and the generated nucleuses keep on growing before the nanocrystals are merged.
- the complete coalescence phase all nanocrystals are merged to form a film.
- the flash memory device has the difficulty in performing high-speed programming and the deterioration of the thermal stability.
- the present invention provides a polysilicon film having small, uniform, nano-size grains less than 10 nm, and a method of forming the same.
- the present invention provides a polysilicon film having small, uniform, nano-size grains less than 10 nm that is obtained through suppressing the continuous grain growth by supplying an impurity gas in a growth dominated phase and a complete coalescence phase during forming the polysilicon film, and a method of forming the same.
- the present invention provides a flash memory device using a polysilicon flim, which has small, uniform, nano-size grains less than 10 nm, as a floating gate, and a method of forming the same.
- a polysilicon film includes a plurality of polysilicon layers stacked to each other, wherein each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains.
- the grain may have a size of approximately 5 nm to approximately 10 nm.
- the impurity atoms may include nitrogen atoms or oxygen atoms, or both.
- a method of manufacturing a polysilicon film includes forming a polysilicon layer including a plurality of grains by supplying a silicon source gas, and providing impurity atoms into boundaries of the grains by supplying an impurity gas.
- the impurity gas may be supplied after the supplying of the silicon source gas is stopped.
- the silicon source gas may be purged before the impurity gas is supplied.
- the impurity gas and the silicon source gas may be simultaneously supplied.
- Forming the polysilicon layer and providing the impurity atoms may be performed at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
- the impurity gas may use a gas including nitrogen atoms or oxygen atoms, or both.
- a flash memory device includes a gate electrode including a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer and a control gate, which is formed over a certain region of a semiconductor substrate, and source/drain junction regions formed at both sides of the gate electrode in the semiconductor substrate, wherein the floating gate is formed by stacking a plurality of polysilicon layers, and each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains.
- the grain may have a size of approximately 5 nm to approximately 10 nm.
- the impurity atoms may include nitrogen atoms or oxygen atoms, or both.
- a method of manufacturing a flash memory device includes forming a tunnel insulation layer over a semiconductor substrate and forming a polysilicon film containing impurities in boundaries of grains, patterning the polysilicon film to form a resultant structure, forming a dielectric layer and a conductive layer over a whole surface of the resultant structure, patterning the conductive layer, dielectric layer, the polysilicon film and the tunnel insulation layer to form a gate electrode incuding a stack structure of a floating gate and a control gate, and forming junction regions by injecting impurity ions into the semiconductor substrate at both sides of the gate electrode.
- Forming the polysilicon layer and providing the impurity atoms may be performed at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
- the impurity gas may use a gas including nitrogen atoms or oxygen atoms, or both.
- the impurity gas is supplied to provide a lot of impurities into boundaries of grains, thereby suppressing the continuous growth of grains and forming the polysilicon film having small, uniform, nano-size grains that is less than 10 nm.
- the impurities existing in the boundaries suppresses the growth of grains after depositing the polysilicon film in a desired thickness or during a thermal budget.
- FIGs. 1 to 5 illustrate cross-sectional views of a method of forming a polysilicon film in accordance with an embodiment of the present invention
- FIG. 6 is a flow chart illustrating a method of forming the polysilicon film in accordance with the embodiment of the present invention.
- FIG. 7 illustrates a cross-sectional view of a flash memory device in accordance with an embodiment of the present invention. Best Mode for Carrying Out the Invention
- FIGs. 1 to 5 illustrate cross-sectional views of a method of forming a polysilicon film in accordance with an embodiment of the present invention
- FIG. 6 is a flow chart illustrating a method of forming the polysilicon film.
- a semiconductor substrate 110 including a certain structure formed thereon is loaded into a chmical vapor deposition (CVD) chamber such as a thermal CVD chamber, a low-pressure chemical vapor deposition (LPCVD) chamber or a plasma-enhanced chemical vapor deposition (PECVD) chamber in step SlOO.
- a silicon source gas is supplied to the chamber to form a first polysilicon layer 120A in step S200.
- the first polysilicon layer 120A is formed in conditions of increasing nucleus density, e.g., at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
- the silicon source gas includes SiH 4 , Si 2 H 6 or Si 2 H 2 Cl 2 .
- stable nucleuses can be generated after silicon adatom reaches onto the surface of the semiconductor substrate 110 and the generated nucleuses grow to nanocrystals and then grains 130A while new nucleuses are continuously generated.
- Grain boundaries 140A are formed between the grains 130A.
- a deposition thickness of the first polysilicon layer 120A is controlled by an inflow amount and time of the silicon source gas supplied to the chamber. For instance, the grain 130A grows in size of approximately 5 nm to approximately 10 nm and the first polysilicon layer 120A is formed in thickness of approximately 5 nm to approximately 10 nm that is substantially the same as the size of the grain 130A.
- the inflow of the silicon source gas is stopped and an impurity gas is supplied in step S300.
- a purge process may be performed using, e.g., a purge gas or an exhaust gas.
- the impurity gas may use a gas containing one of nitrogen atoms, oxide atoms and a combination thereof.
- the impurity gas includes one of NH 3 , O 2 , N 2 O and a combination of.
- an impurity atom 150A including one of nitrogen atom, oxide atom and a combination thereof may be contained in the grain boundary 140A.
- the impurity atom 150A is contained in the grain boundary 140A, the growth of the grain 130A is suppressed and thus the grain 130A maintains a nano size of, e.g., approximatley 5 nm to approximately 10 nm.
- the impurity gas is supplied at the temperature ranging from approximately 450 0C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, which are substantially the same conditions as the first polysilicon layer 120A is deposited. Since the content of the impurities supplied to the grain boundary 140A can be controlled according to the temperature and pressure, the temperature and the pressure are adjusted depending on a desired grain size to be obtained by containing the impurities. In addition, by controlling the inflow amount and time of the impurity gas, the impurity atom 150A is contained into the grain boundary 140A unless a layer is formed by the impurity gas.
- step S400 it is determined whether a desired thickness of the polysilicon film is obatined. If the desired thickness is not acquired, the silicon source gas is supplied again to form a second polysilicon layer 120B.
- the second polysilicon layer 120B may be formed in substantially the same conditions as the first polysilicon layer 120A is formed. That is, the second polysilicon layer 120B is formed at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, thereby increasing the nucleus density.
- a thickness of the second polysilicon layer 120B is adjusted by controlling an inflow amount and time of the silicon source gas and a grain 130B grows within the second polysilicon layer 120B, forming a grain boundary 140B. It is preferable that the second polysilicon layer 120B has substantially the same thickness as the size of the grain 130B. For instance, the grain 130B grows in a size of approximately 5 nm to approximately 10 nm and the second polysilicon layer 120B is deposited to have a thickness of approximately 5 nm to approximately 10 nm.
- the grain 130A of the first polysilicon layer 120A does not continuously grow with the grain 130B of the second polysilicon layer 120B by the impurity atom 150A contained in the boundary 140A, so that the size of the grain 130A does not increase anymore.
- the inflow of the silicon source gas is stopped and an impurity gas is supplied, so that an impurity atom 150B is contained in the grain boundary 140B of the second polysilicon layer 120B in step S300.
- the impurity gas supplied to provide the impurity atom 150B into the grain boundary 130B uses a gas containing one of nitrogen atoms, oxide atoms and a combination thereof.
- the impurity gas includes one of NH 3 , O 2 , N 2 O and a combination of.
- the impurity atom 150B including one of nitrogen atom, oxide atom and a combination thereof is contained in the grain boundary 140B. Since the impurity atom 150B is contained in the grain boundary 140B, the growth of the grain 130B is suppressed in subsequent processes.
- the processes for growing the polysilicon layer and providing the impurity atom into the grain boundary are iterated by repeatedly supplying the silicon source gas and the impurity gas, thereby forming a polysilicon film 160 having a desired thickness in step S400.
- the impurity gas is supplied when coalescence of the grains starts, i.e., the polysilicon layers are deposited.
- the impurity gas may be supplied when the nanocrystal is formed not when the coalescence of the grains starts.
- the silicon source gas and the impurity gas may be simultaneously supplied to provide the impurity atom into the grain boundary. In this case, it is possible to mainly oxidize the grain boundary using an energy barrier between the grain and the grain boundary when a small amount of impurity gas is supplied.
- an amount of impurity atoms existing inside a polysilcon crystalloid may be increased.
- the impurity atoms may exist in an undesired part of the crystalloid not in the grain boundary. Therefore, compared to simultaneously supplying the silicon source gas and the impurity gas, it is more effective to supply the impurity gas after stopping the supply of the silicon source gas.
- the polysilicon film that is formed in size of 5 nm to 10 nm as illustrated above may be used as a floating gate of a flash memory device, thereby increasing a program and erase speed, improving thermal stability and enhancing the reliability of the device.
- the flash memory device that uses the polysilicon film having nano-size grains as its floating gate.
- FIG. 7 illustrates a cross-sectional view of a flash memory device empolying a polysilicon film that has nano-size grains and grain boundaries containing impurities therein.
- the flash memory device includes a gate electrode 200 having a stack structure of a tunnel insulation layer 210 formed over a certain region of a sim- conductor substrate 110, a floating gate 220 formed of a polysilicon film having nano- size grains whose boundaries contain impurity atoms, a dielectric layer 230 and a control gate 240, and source/drain junction regions 250 formed at both sides of the gate electrode 200 in the semiconductor substrate 110.
- the semiconductor substrate 110 is formed of one selected from a group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP and a combination thereof.
- the tunnel insulation layer 210 is formed of one selected from a group consisting of
- the tunnel insulation layer 210 may include a structure formed by sequentially stacking two or more materials selected from the above materials.
- the SiO 2 layer may be formed by oxidation such as dry oxidation performed using an O 2 gas at the temperature of approximately 1000 0 C to ap- proximately 1100 0 C, wet oxidation performed in moisture atmosphere at the temperature of approximately 1000 0 C to approximately 1100 0 C, HCl oxidation using a mixed gas of an O 2 gas and a HCl gas, oxidation using a mixed gas of an O 2 gas and a C 2 H 3 Cl 3 gas, oxidation using a mixed gas of an O 2 gas and a C 2 H 2 Cl 2 gas, and so on.
- oxidation such as dry oxidation performed using an O 2 gas at the temperature of approximately 1000 0 C to ap- proximately 1100 0 C, wet oxidation performed in moisture atmosphere at the temperature of approximately 1000 0 C to approximately 1100 0 C, HCl oxidation using a mixed gas of an O 2 gas and a HCl gas, oxidation using a mixed gas of an O
- the material having high permittivity may include one of HfO 2 , ZrO 2 , Al 2 O 3 , Ta 2 O 5 , hafnium silicate, zirconium silicate and a combination thereof to form a layer having the high permittivity by performing an atomic layer deposition method.
- the floating gate 220 is formed using the polysilicon film having grains whose boundaries contain impurity atoms, wherein a size of the grain ranges from approximately 5 nm to approximately 10 nm.
- the polysilicon film for forming the floating gate 220 is made by stacking a plurality of polysilicon layers and each of the polysilicon layers contains the impurity atoms in its grain boundaries. For this, a silicon source gas and an impurity gas are repeatedly supplied to form the polysilicon film having a desired thickness.
- the polysilicon layer is formed by supplying the silicon source gas at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, wherein the silicon source gas includes one of SiH 4 , Si 2 H 6 , Si 2 H 2 Cl 2 and a combination thereof. It is preferable that the thickness of the polysilicon layer is controlled to a grain size by adjusting an inflow amount and time of the silicon source gas. Then, the inflow of the silicon source gas is stopped at the time of coalescence of the grains and the impurity gas is supplied at the temperature ranging from approximately 450 0 C to approximately 800 0 C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
- the temperature and pressure may be substantially the same as those required for performing a process of depositing polysilicon. Since it is possible to control the content of impurities provided into the grain boundaries by adjusting the temperature and the pressure, the temperature and the pressure are adjusted according to a desired grain size obtained by containing the impurities. Furthermore, by adjusting the inflow amount and time of the impurity gas, the impurity atoms are contained in the grain boundaries unless a film is formed by the impurity gas. By this way, the impurity atoms are contained in the grain boundaries of the polysilicon layer and thus growth of grains is suppressed in subsequent processes.
- the dielectric layer 230 may use an ONO layer or, like the tunnel insulation layer
- the dielectric layer 230 may be formed to have a thickness greater than that of the tunnel insulation layer 210.
- the control gate 240 includes a conductive layer such as a polysilicon layer, a metal layer of W, Pt or Al, a metal nitride layer such as a TiN layer, a metal suicide layer made of refractory metal such as Co, Ni, Ti, Hf and Pt, or a stack layer thereof.
- the control gate 240 may be formed by stacking a polysilicon layer and a metal suicide layer, or a polysilicon layer and a metal layer.
- the polysilicon layer may be formed using a silicon source gas such as a SiH 2 Cl 2 gas and an impurity source gas such as a PH 3 gas, and performing an LPCVD method.
- the source/drain junction regions 250 are formed by injecting an n-type or p-type impurity into the semiconductor substrate 110 according to a desired type of a flash memory cell.
- the source/drain junction regions 250 may be formed with a lightly doped drain (LDD) region slightly formed performing a low concentration ion injection process and a heavily doped drain region deeply formed performing a high concentration ion injection process, wherein the heavily doped drain region is formed after the LDD region is formed. It is possible to effectively suppress the occurrence of a breakdown although a high voltage is supplied to the source/drain junction regions 250 since the source/drain junction regions 250 include the LDD region.
- LDD lightly doped drain
- a halo region may be formed beneath the heavily doped drain region and the LDD region by doping an impurity of a conductive type opposite to the conductive type of the source/drain junction regions 250.
- spacers 260 may be formed on sidewalls of the gate electrode 200.
- the spacers 260 may be formed before forming the heavily doped drain region when the source/drain junction region 250 includes the LDD region and the heavily doped drain region.
- the flash memory device in accordance with the embodiment of the present invention may be a NOR-type flash memory device or a NAND-type flash memory device according to a manufacturing method and the layout of peripheral circuits.
- the NAND-type flash memory device may be formed using various methods such as a self align shallow trench isolation (SASTI) method or a self align floating gate (SAFG) method.
- SASTI self align shallow trench isolation
- SAFG self align floating gate
Abstract
Provided are a polysilicon film and a method of manufacturing the same, and a flash memory device employing the polysilicon film and a method of manufacturing the flash memory device. After the polysilicon film grows to a thickness that is the same as a grain size, an impurity gas is supplied to provide a lot of impurities into boundaries of grains, thereby suppressing the continuous growth of grains and forming the polysilicon film having small, uniform, nano-size grains whose size is less than 10 nm. The impurities existing in the boundaries suppress the growth of grains in subsequent processes. By using the polysilicon film as a floating gate of the flash memory device, it is possible to increase a program or erase speed and improve thermal stability, thereby enhancing the reliabilty of the device.
Description
Description
POLYSILICON FILM AND METHOD OF FORMING THE SAME, FLASH MEMORY DEVICE AND MANUFACTURING
METHOD USING THE SAME
Technical Field
[1] The present invention relates to a polysilicon film and a method of manufacturing the same, and more particularly, to a polysilicon film having nano-size grains and a method of forming the same, and a flash memory device employing the polysilicon film and a method of manufacturing the flash memory device. Background Art
[2] A flash memory device is a non- volatile memory device that can program and erase data, and read out the programmed data. Thus, the flash memory device has a cell structure that includes a gate electrode insulated from a semiconductor substrate by a tunnel oxide layer and formed with a dielectric layer interposed between a floating gate and a control gate, and source/drain junction regions disposed at both sides of the gate electrode.
[3] The flash memory device is programmed and erased performing an operation of injecting charge onto the floating gate and pulling the charge off the floating gate. That is, a positive voltage applied to the control gate is coupled to the floating gate and thus the flash memory device is programed by electrons that are captured into the floating gate through the tunnel oxide layer from the substrate through Fowler-Nordheim (FN) tunneling or hot-carrier injection. On the other hand, in the erase operation, the electrons within the floating gate are moved into the substrate by a negative voltage applied to the control gate.
[4] The floating gate of the flash memory device may include a polysilicon film.
However, as a design rule decreases, in a flash memory device having a design rule less than 40 nm, it is required to increase the number of grains in a polysilicon film used as a floating gate as well as increasing a tunneling field in order to perform a high-speed program by reducing a threshold voltage. For this purpose, the grain size of the polysilicon film should be reduced. As the grain size is reduced, the number of grain boundaries is increased and thus an erasing speed of the flash memory device becomes high. That is, a programming speed and the erasing speed of the flash memory device can be improved by reducing the grain size of the polysilicon film used as the floating gate. Furthermore, as the grain size of the polysilicon film is reduced to especially a nano size, thermal stability of the floating gate is enhanced and thus the performance of the device can be improved.
[5] The polysilicon film is formed through several phases such as an incubation phase, a nucleation and growth phase, a growth dominated phase, and a complete coalescence phase. In the incubation phase, silicon adatom reaches onto a surface of the tunnel oxide layer and a first stable nucleus is generated. In the nucleation and growth phase, new nucleuses are consecutively generated while the previously generated nucleuses grow into nanocrystals. In the growth dominated phase, the generation of new nucleuses is stopped and the generated nucleuses keep on growing before the nanocrystals are merged. In the complete coalescence phase, all nanocrystals are merged to form a film.
[6] In order to reduce the grain size of the polysilicon film, until the coalescence occurs, it is required to minimize a size of an individual grain by increasing nucleus generation density in the nucleation and growth phase. However, the grain growth is continued through the nucleation and growth phase, the growth dominated phase and the complete coalescence phase. The grain growth is continued during the film being deposited after the coalescence occured. After the deposition is even completed, during a post thermal process that is performed at the temperature of 900 0C for 1 lour, the grain growth is continued by a solid phase diffusion phenomenon, thereby increasing the grain size.
[7] As the grain size of the polysilicon film is continuously increased as described above, the flash memory device has the difficulty in performing high-speed programming and the deterioration of the thermal stability.
Disclosure of Invention
Technical Problem
[8] The present invention provides a polysilicon film having small, uniform, nano-size grains less than 10 nm, and a method of forming the same.
[9] The present invention provides a polysilicon film having small, uniform, nano-size grains less than 10 nm that is obtained through suppressing the continuous grain growth by supplying an impurity gas in a growth dominated phase and a complete coalescence phase during forming the polysilicon film, and a method of forming the same.
[10] The present invention provides a flash memory device using a polysilicon flim, which has small, uniform, nano-size grains less than 10 nm, as a floating gate, and a method of forming the same. Technical Solution
[11] In accordance with one aspect of the present invention, a polysilicon film includes a plurality of polysilicon layers stacked to each other, wherein each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains.
[12] The grain may have a size of approximately 5 nm to approximately 10 nm.
[13] The impurity atoms may include nitrogen atoms or oxygen atoms, or both.
[14] In accordance with another aspect of the present invention, a method of manufacturing a polysilicon film includes forming a polysilicon layer including a plurality of grains by supplying a silicon source gas, and providing impurity atoms into boundaries of the grains by supplying an impurity gas.
[15] The impurity gas may be supplied after the supplying of the silicon source gas is stopped.
[16] The silicon source gas may be purged before the impurity gas is supplied.
[17] The impurity gas and the silicon source gas may be simultaneously supplied.
[18] supplying the silicon source gas and supplying the impurity gas may be repeated.
[19] Forming the polysilicon layer and providing the impurity atoms may be performed at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
[20] The impurity gas may use a gas including nitrogen atoms or oxygen atoms, or both.
[21] In accordance with still another aspect of the present invention, a flash memory device includes a gate electrode including a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer and a control gate, which is formed over a certain region of a semiconductor substrate, and source/drain junction regions formed at both sides of the gate electrode in the semiconductor substrate, wherein the floating gate is formed by stacking a plurality of polysilicon layers, and each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains.
[22] The grain may have a size of approximately 5 nm to approximately 10 nm.
[23] The impurity atoms may include nitrogen atoms or oxygen atoms, or both.
[24] In accordance with still another aspect of the present invention, a method of manufacturing a flash memory device includes forming a tunnel insulation layer over a semiconductor substrate and forming a polysilicon film containing impurities in boundaries of grains, patterning the polysilicon film to form a resultant structure, forming a dielectric layer and a conductive layer over a whole surface of the resultant structure, patterning the conductive layer, dielectric layer, the polysilicon film and the tunnel insulation layer to form a gate electrode incuding a stack structure of a floating gate and a control gate, and forming junction regions by injecting impurity ions into the semiconductor substrate at both sides of the gate electrode.
[25] Forming the polysilicon film may include forming a polysilicon layer including a plurality of grains by supplying a silicon source gas, and stopping the supplying of the silicon source gas and supplying an impurity gas to provide impurity atoms into the boundaries of the grains.
[26] Forming the polysilicon film may include forming a polysilicon layer including a plurality of grains by supplying a silicon source gas, and supplying the silicon source gas and an impurity gas to provide impurity atoms into the boundaries of the grains.
[27] Forming the polysilicon layer and providing the impurity atoms may be performed at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
[28] The impurity gas may use a gas including nitrogen atoms or oxygen atoms, or both.
Advantageous Effects
[29] In accordance with the present invention, in the growth dominated phase or the complete coalescence phase during forming the polysilicon film, i.e., after the polysilicon film grows to a thickness that is the same as a grain size, the impurity gas is supplied to provide a lot of impurities into boundaries of grains, thereby suppressing the continuous growth of grains and forming the polysilicon film having small, uniform, nano-size grains that is less than 10 nm. The impurities existing in the boundaries suppresses the growth of grains after depositing the polysilicon film in a desired thickness or during a thermal budget.
[30] By using the polysilicon film as a floating gate of a flash memory device, it is possible to increase a program or erase speed and improve thermal stability, thereby enhancing the reliabilty of the device. Brief Description of the Drawings
[31] FIGs. 1 to 5 illustrate cross-sectional views of a method of forming a polysilicon film in accordance with an embodiment of the present invention;
[32] FIG. 6 is a flow chart illustrating a method of forming the polysilicon film in accordance with the embodiment of the present invention; and
[33] FIG. 7 illustrates a cross-sectional view of a flash memory device in accordance with an embodiment of the present invention. Best Mode for Carrying Out the Invention
[34] Hereinafter, specific embodiments will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the figures, the dimensions of layers and regions are exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout. It will also be understood that when a layer, a film, a region or a plate is referred to as being 'on' another one, it can be directly on the other one, or one or more intervening layers, films, regions or plates may also be present.
[35] FIGs. 1 to 5 illustrate cross-sectional views of a method of forming a polysilicon film in accordance with an embodiment of the present invention, and FIG. 6 is a flow chart illustrating a method of forming the polysilicon film.
[36] Referring to FIGs. 1 and 6, a semiconductor substrate 110 including a certain structure formed thereon is loaded into a chmical vapor deposition (CVD) chamber such as a thermal CVD chamber, a low-pressure chemical vapor deposition (LPCVD) chamber or a plasma-enhanced chemical vapor deposition (PECVD) chamber in step SlOO. Then, a silicon source gas is supplied to the chamber to form a first polysilicon layer 120A in step S200. The first polysilicon layer 120A is formed in conditions of increasing nucleus density, e.g., at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr. Herein, the silicon source gas includes SiH4, Si2H6 or Si2H2Cl2. In those conditions, stable nucleuses can be generated after silicon adatom reaches onto the surface of the semiconductor substrate 110 and the generated nucleuses grow to nanocrystals and then grains 130A while new nucleuses are continuously generated. Grain boundaries 140A are formed between the grains 130A. A deposition thickness of the first polysilicon layer 120A is controlled by an inflow amount and time of the silicon source gas supplied to the chamber. For instance, the grain 130A grows in size of approximately 5 nm to approximately 10 nm and the first polysilicon layer 120A is formed in thickness of approximately 5 nm to approximately 10 nm that is substantially the same as the size of the grain 130A.
[37] Referring to FIGs. 2 and 6, after the grain 130A is formed in a certain size and the first polysilicon layer 120A is formed in a thickness identical to the size of the grain 130A and, before the grains 130A are fused each other, the inflow of the silicon source gas is stopped and an impurity gas is supplied in step S300. At this time, to remove the silicon source gas remaining in the chamber, a purge process may be performed using, e.g., a purge gas or an exhaust gas. The impurity gas may use a gas containing one of nitrogen atoms, oxide atoms and a combination thereof. For example, the impurity gas includes one of NH3, O2, N2O and a combination of. The reason the impurity gas uses the nitrogen atoms or the oxide atoms, those atoms do not damage a gate oxide layer and can be combined with the polysilicon without making bad influence on electrical performance of a layer although they are diffused into and exist within crystalloid. Besides the nitrogen or oxide atoms, other atoms may be used if they can maintain the performance of the polysilicon film. By the supplied impurity gas, an impurity atom 150A including one of nitrogen atom, oxide atom and a combination thereof may be contained in the grain boundary 140A. Since the impurity atom 150A is contained in the grain boundary 140A, the growth of the grain 130A is suppressed and thus the grain 130A maintains a nano size of, e.g., approximatley 5 nm to approximately 10
nm. The impurity gas is supplied at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, which are substantially the same conditions as the first polysilicon layer 120A is deposited. Since the content of the impurities supplied to the grain boundary 140A can be controlled according to the temperature and pressure, the temperature and the pressure are adjusted depending on a desired grain size to be obtained by containing the impurities. In addition, by controlling the inflow amount and time of the impurity gas, the impurity atom 150A is contained into the grain boundary 140A unless a layer is formed by the impurity gas.
[38] Referring to FIGs. 3 and 6, in step S400, it is determined whether a desired thickness of the polysilicon film is obatined. If the desired thickness is not acquired, the silicon source gas is supplied again to form a second polysilicon layer 120B. The second polysilicon layer 120B may be formed in substantially the same conditions as the first polysilicon layer 120A is formed. That is, the second polysilicon layer 120B is formed at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, thereby increasing the nucleus density. A thickness of the second polysilicon layer 120B is adjusted by controlling an inflow amount and time of the silicon source gas and a grain 130B grows within the second polysilicon layer 120B, forming a grain boundary 140B. It is preferable that the second polysilicon layer 120B has substantially the same thickness as the size of the grain 130B. For instance, the grain 130B grows in a size of approximately 5 nm to approximately 10 nm and the second polysilicon layer 120B is deposited to have a thickness of approximately 5 nm to approximately 10 nm. At this time, the grain 130A of the first polysilicon layer 120A does not continuously grow with the grain 130B of the second polysilicon layer 120B by the impurity atom 150A contained in the boundary 140A, so that the size of the grain 130A does not increase anymore.
[39] Referring to FIGs. 4 and 6, the inflow of the silicon source gas is stopped and an impurity gas is supplied, so that an impurity atom 150B is contained in the grain boundary 140B of the second polysilicon layer 120B in step S300. The impurity gas supplied to provide the impurity atom 150B into the grain boundary 130B uses a gas containing one of nitrogen atoms, oxide atoms and a combination thereof. For example, the impurity gas includes one of NH3, O2, N2O and a combination of. By the supplied impurity gas, the impurity atom 150B including one of nitrogen atom, oxide atom and a combination thereof is contained in the grain boundary 140B. Since the impurity atom 150B is contained in the grain boundary 140B, the growth of the grain 130B is suppressed in subsequent processes.
[40] Referring to FIGs. 5 and 6, the processes for growing the polysilicon layer and
providing the impurity atom into the grain boundary are iterated by repeatedly supplying the silicon source gas and the impurity gas, thereby forming a polysilicon film 160 having a desired thickness in step S400.
[41] In the above embodiment, the impurity gas is supplied when coalescence of the grains starts, i.e., the polysilicon layers are deposited. However, in order to obtain a smaller size of grains, the impurity gas may be supplied when the nanocrystal is formed not when the coalescence of the grains starts. Furthermore, the silicon source gas and the impurity gas may be simultaneously supplied to provide the impurity atom into the grain boundary. In this case, it is possible to mainly oxidize the grain boundary using an energy barrier between the grain and the grain boundary when a small amount of impurity gas is supplied. However, in case of simultaneously supplying the silicon source gas and the impurity gas, an amount of impurity atoms existing inside a polysilcon crystalloid may be increased. That is, the impurity atoms may exist in an undesired part of the crystalloid not in the grain boundary. Therefore, compared to simultaneously supplying the silicon source gas and the impurity gas, it is more effective to supply the impurity gas after stopping the supply of the silicon source gas.
[42] The polysilicon film that is formed in size of 5 nm to 10 nm as illustrated above may be used as a floating gate of a flash memory device, thereby increasing a program and erase speed, improving thermal stability and enhancing the reliability of the device. Hereinafter, there will be described the flash memory device that uses the polysilicon film having nano-size grains as its floating gate.
[43] FIG. 7 illustrates a cross-sectional view of a flash memory device empolying a polysilicon film that has nano-size grains and grain boundaries containing impurities therein.
[44] Referring to FIG. 7, the flash memory device includes a gate electrode 200 having a stack structure of a tunnel insulation layer 210 formed over a certain region of a sim- conductor substrate 110, a floating gate 220 formed of a polysilicon film having nano- size grains whose boundaries contain impurity atoms, a dielectric layer 230 and a control gate 240, and source/drain junction regions 250 formed at both sides of the gate electrode 200 in the semiconductor substrate 110.
[45] The semiconductor substrate 110 is formed of one selected from a group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP and a combination thereof.
[46] The tunnel insulation layer 210 is formed of one selected from a group consisting of
SiO2, SiON, Si3N4, GexOyNz, GexSiyOz, a material having high permittivity and a combination thereof. For instance, the tunnel insulation layer 210 may include a structure formed by sequentially stacking two or more materials selected from the above materials. Herein, the SiO2 layer may be formed by oxidation such as dry oxidation performed using an O2 gas at the temperature of approximately 1000 0C to ap-
proximately 1100 0C, wet oxidation performed in moisture atmosphere at the temperature of approximately 1000 0C to approximately 1100 0C, HCl oxidation using a mixed gas of an O2 gas and a HCl gas, oxidation using a mixed gas of an O2 gas and a C2H3Cl3 gas, oxidation using a mixed gas of an O2 gas and a C2H2Cl2 gas, and so on. The material having high permittivity may include one of HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate and a combination thereof to form a layer having the high permittivity by performing an atomic layer deposition method.
[47] The floating gate 220 is formed using the polysilicon film having grains whose boundaries contain impurity atoms, wherein a size of the grain ranges from approximately 5 nm to approximately 10 nm. The polysilicon film for forming the floating gate 220 is made by stacking a plurality of polysilicon layers and each of the polysilicon layers contains the impurity atoms in its grain boundaries. For this, a silicon source gas and an impurity gas are repeatedly supplied to form the polysilicon film having a desired thickness. The polysilicon layer is formed by supplying the silicon source gas at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr, wherein the silicon source gas includes one of SiH4, Si2H6, Si2H2Cl2 and a combination thereof. It is preferable that the thickness of the polysilicon layer is controlled to a grain size by adjusting an inflow amount and time of the silicon source gas. Then, the inflow of the silicon source gas is stopped at the time of coalescence of the grains and the impurity gas is supplied at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr. At this time, the temperature and pressure may be substantially the same as those required for performing a process of depositing polysilicon. Since it is possible to control the content of impurities provided into the grain boundaries by adjusting the temperature and the pressure, the temperature and the pressure are adjusted according to a desired grain size obtained by containing the impurities. Furthermore, by adjusting the inflow amount and time of the impurity gas, the impurity atoms are contained in the grain boundaries unless a film is formed by the impurity gas. By this way, the impurity atoms are contained in the grain boundaries of the polysilicon layer and thus growth of grains is suppressed in subsequent processes.
[48] The dielectric layer 230 may use an ONO layer or, like the tunnel insulation layer
210, it may use one selected from a group consisting of SiO2, SiON, Si3N4, GexOyNz, GexSiyOz, a material having high permittivity and a combination thereof. The dielectric layer 230 may be formed to have a thickness greater than that of the tunnel insulation layer 210.
[49] The control gate 240 includes a conductive layer such as a polysilicon layer, a metal layer of W, Pt or Al, a metal nitride layer such as a TiN layer, a metal suicide layer
made of refractory metal such as Co, Ni, Ti, Hf and Pt, or a stack layer thereof. For instance, the control gate 240 may be formed by stacking a polysilicon layer and a metal suicide layer, or a polysilicon layer and a metal layer. Herein, the polysilicon layer may be formed using a silicon source gas such as a SiH2Cl2 gas and an impurity source gas such as a PH3 gas, and performing an LPCVD method.
[50] The source/drain junction regions 250 are formed by injecting an n-type or p-type impurity into the semiconductor substrate 110 according to a desired type of a flash memory cell. The source/drain junction regions 250 may be formed with a lightly doped drain (LDD) region slightly formed performing a low concentration ion injection process and a heavily doped drain region deeply formed performing a high concentration ion injection process, wherein the heavily doped drain region is formed after the LDD region is formed. It is possible to effectively suppress the occurrence of a breakdown although a high voltage is supplied to the source/drain junction regions 250 since the source/drain junction regions 250 include the LDD region. In addition, a halo region may be formed beneath the heavily doped drain region and the LDD region by doping an impurity of a conductive type opposite to the conductive type of the source/drain junction regions 250. By including the halo region, it is possible to effectively maintain thermal electrons in a program operation.
[51] Furthermore, spacers 260 may be formed on sidewalls of the gate electrode 200. The spacers 260 may be formed before forming the heavily doped drain region when the source/drain junction region 250 includes the LDD region and the heavily doped drain region.
[52] The flash memory device in accordance with the embodiment of the present invention may be a NOR-type flash memory device or a NAND-type flash memory device according to a manufacturing method and the layout of peripheral circuits. The NAND-type flash memory device may be formed using various methods such as a self align shallow trench isolation (SASTI) method or a self align floating gate (SAFG) method.
[53] Although the present invention has been described with reference to the specific embodiments, they are not limited thereto. Therefore, it will be readily understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present invention defined by the appended claims.
[54]
Claims
Claims
[I] A polysilicon film, comprising: a plurality of polysilicon layers stacked to each other, wherein each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains. [2] The polysilicon film of claim 1, wherein the grain has a size of approximately 5 nm to approximately 10 nm. [3] The polysilicon film of claim 1, wherein the impurity atoms include nitrogen atoms or oxygen atoms, or both. [4] A method of manufacturing a polysilicon film, the method comprising: forming a polysilicon layer including a plurality of grains by supplying a silicon source gas; and providing impurity atoms into boundaries of the grains by supplying an impurity gas. [5] The method of claim 4, wherein the impurity gas is supplied after the supplying of the silicon source gas is stopped. [6] The method of claim 5, wherein the silicon source gas is purged before the impurity gas is supplied. [7] The method of claim 4, wherein the impurity gas and the silicon source gas are simultaneously supplied. [8] The method of claim 4, wherein supplying the silicon source gas and supplying the impurity gas are repeated. [9] The method of claim 4, wherein forming the polysilicon layer and providing the impurity atoms are performed at the temperature ranging from approximately
450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr. [10] The method of claim 4, wherein the impurity gas includes a gas including nitrogen atoms or oxygen atoms, or both.
[I I] A flash memory device, comprising: a gate electrode including a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer and a control gate, which is formed over a certain region of a semiconductor substrate; and source/drain junction regions formed at both sides of the gate electrode in the semiconductor substrate, wherein the floating gate is formed by stacking a plurality of polysilicon layers, and each of the polysilicon layers includes a plurality of grains and contains impurity atoms in boundaries of the grains to suppress the growth of the grains.
[12] The flash memory device of claim 11, wherein the grain has a size of approximately 5 nm to approximately 10 nm.
[13] The flash memory device of claim 11, wherein the impurity atoms include nitrogen atoms or oxygen atoms, or both.
[14] A method of manufacturing a flash memory device, the method comprising: forming a tunnel insulation layer over a semiconductor substrate and forming a polysilicon film containing impurities in boundaries of grains; patterning the polysilicon film to form a resultant structure; forming a dielectric layer and a conductive layer over a whole surface of the resultant structure; patterning the conductive layer, dielectric layer, the polysilicon film and the tunnel insulation layer to form a gate electrode incuding a stack structure of a floating gate and a control gate; and forming junction regions by injecting impurity ions into the semiconductor substrate at both sides of the gate electrode.
[15] The method of claim 14, wherein forming the polysilicon film comprises: forming a polysilicon layer including a plurality of grains by supplying a silicon source gas; and stopping the supplying of the silicon source gas and supplying an impurity gas to provide impurity atoms into the boundaries of the grains.
[16] The method of claim 14, wherein forming the polysilicon film comprises: forming a polysilicon layer including a plurality of grains by supplying a silicon source gas; and supplying the silicon source gas and an impurity gas to provide impurity atoms into the boundaries of the grains.
[17] The method of claim 15 or 16, wherein forming the polysilicon layer and providing the impurity atoms are performed at the temperature ranging from approximately 450 0C to approximately 800 0C and in the pressure of approximately 1E-5 Torr to approximately 760 Torr.
[18] The method of claim 15 or 16, wherein the impurity gas uses a gas including nitrogen atoms or oxygen atoms, or both.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110159674A1 (en) * | 2009-12-30 | 2011-06-30 | Hynix Semiconductor Inc. | Method of Manufacturing Nonvolatile Memory Devices |
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TWI582963B (en) * | 2015-08-28 | 2017-05-11 | 旺宏電子股份有限公司 | Memory device and method for fabricating the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5441904A (en) * | 1993-11-16 | 1995-08-15 | Hyundai Electronics Industries, Co., Ltd. | Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries |
US20040266212A1 (en) * | 2003-06-30 | 2004-12-30 | Lee Chang Jin | Method for manufacturing semiconductor device |
KR20050002085A (en) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | Method for forming a floating gate in flash memory device |
JP2006120663A (en) * | 2004-10-19 | 2006-05-11 | Sharp Corp | Non-volatile semiconductor storage and manufacturing method thereof |
KR20060099694A (en) * | 2005-03-14 | 2006-09-20 | 삼성전자주식회사 | Semiconductor substrate having gettering site layer and method of forming the same |
-
2007
- 2007-09-27 KR KR1020070097199A patent/KR20090032196A/en not_active Application Discontinuation
-
2008
- 2008-09-26 TW TW097137376A patent/TW200926270A/en unknown
- 2008-09-26 WO PCT/KR2008/005706 patent/WO2009041781A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5441904A (en) * | 1993-11-16 | 1995-08-15 | Hyundai Electronics Industries, Co., Ltd. | Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries |
US20040266212A1 (en) * | 2003-06-30 | 2004-12-30 | Lee Chang Jin | Method for manufacturing semiconductor device |
KR20050002085A (en) * | 2003-06-30 | 2005-01-07 | 주식회사 하이닉스반도체 | Method for forming a floating gate in flash memory device |
JP2006120663A (en) * | 2004-10-19 | 2006-05-11 | Sharp Corp | Non-volatile semiconductor storage and manufacturing method thereof |
KR20060099694A (en) * | 2005-03-14 | 2006-09-20 | 삼성전자주식회사 | Semiconductor substrate having gettering site layer and method of forming the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110159674A1 (en) * | 2009-12-30 | 2011-06-30 | Hynix Semiconductor Inc. | Method of Manufacturing Nonvolatile Memory Devices |
Also Published As
Publication number | Publication date |
---|---|
WO2009041781A3 (en) | 2009-05-28 |
KR20090032196A (en) | 2009-04-01 |
TW200926270A (en) | 2009-06-16 |
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