WO2009097693A8 - Selective broadcasting of data in series connected devices - Google Patents

Selective broadcasting of data in series connected devices Download PDF

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Publication number
WO2009097693A8
WO2009097693A8 PCT/CA2009/000156 CA2009000156W WO2009097693A8 WO 2009097693 A8 WO2009097693 A8 WO 2009097693A8 CA 2009000156 W CA2009000156 W CA 2009000156W WO 2009097693 A8 WO2009097693 A8 WO 2009097693A8
Authority
WO
WIPO (PCT)
Prior art keywords
devices
command
packet
memory controller
series connected
Prior art date
Application number
PCT/CA2009/000156
Other languages
French (fr)
Other versions
WO2009097693A1 (en
Inventor
Hong Beom Pyeon
Original Assignee
Mosaid Technologies Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Incorporated filed Critical Mosaid Technologies Incorporated
Publication of WO2009097693A1 publication Critical patent/WO2009097693A1/en
Publication of WO2009097693A8 publication Critical patent/WO2009097693A8/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Small-Scale Networks (AREA)
  • Dram (AREA)

Abstract

A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.
PCT/CA2009/000156 2008-02-04 2009-02-06 Selective broadcasting qf data in series connected devices WO2009097693A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2591608P 2008-02-04 2008-02-04
US61/025,916 2008-02-04
US12/254,315 2008-10-20
US12/254,315 US8131913B2 (en) 2008-02-04 2008-10-20 Selective broadcasting of data in series connected devices

Publications (2)

Publication Number Publication Date
WO2009097693A1 WO2009097693A1 (en) 2009-08-13
WO2009097693A8 true WO2009097693A8 (en) 2009-12-10

Family

ID=40932767

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2009/000156 WO2009097693A1 (en) 2008-02-04 2009-02-06 Selective broadcasting qf data in series connected devices

Country Status (4)

Country Link
US (1) US8131913B2 (en)
EP (1) EP2251872B1 (en)
ES (1) ES2478274T3 (en)
WO (1) WO2009097693A1 (en)

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US8943224B2 (en) 2010-03-15 2015-01-27 Rambus Inc. Chip selection in a symmetric interconnection topology
US8572423B1 (en) * 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8856482B2 (en) * 2011-03-11 2014-10-07 Micron Technology, Inc. Systems, devices, memory controllers, and methods for memory initialization
AU2011101297B4 (en) 2011-08-15 2012-06-14 Uniloc Usa, Inc. Remote recognition of an association between remote devices
US11048410B2 (en) 2011-08-24 2021-06-29 Rambus Inc. Distributed procedure execution and file systems on a memory interface
US9098209B2 (en) 2011-08-24 2015-08-04 Rambus Inc. Communication via a memory interface
WO2013028827A1 (en) 2011-08-24 2013-02-28 Rambus Inc. Methods and systems for mapping a peripheral function onto a legacy memory interface
US20130073815A1 (en) * 2011-09-19 2013-03-21 Ronald R. Shea Flexible command packet-header for fragmenting data storage across multiple memory devices and locations
US8797799B2 (en) * 2012-01-05 2014-08-05 Conversant Intellectual Property Management Inc. Device selection schemes in multi chip package NAND flash memory system
JP5624578B2 (en) * 2012-03-23 2014-11-12 株式会社東芝 Memory system
KR20140006344A (en) * 2012-07-04 2014-01-16 에스케이하이닉스 주식회사 Memory system and operating method of memory device included the same
US9286466B2 (en) 2013-03-15 2016-03-15 Uniloc Luxembourg S.A. Registration and authentication of computing devices using a digital skeleton key
US20150089127A1 (en) * 2013-09-23 2015-03-26 Kuljit S. Bains Memory broadcast command
TWI573426B (en) * 2015-02-12 2017-03-01 達創科技股份有限公司 Intelligent luminance system,network apparatus and operating method thereof
US10055343B2 (en) * 2015-12-29 2018-08-21 Memory Technologies Llc Memory storage windows in a memory system
US10140222B1 (en) * 2017-07-06 2018-11-27 Micron Technology, Inc. Interface components
US11966303B2 (en) * 2022-06-02 2024-04-23 Micron Technology, Inc. Memory system failure detection and self recovery of memory dice
CN115174522A (en) * 2022-07-05 2022-10-11 易事特储能科技有限公司 Electronic equipment ID configuration method, device, equipment and readable storage medium

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US5860080A (en) 1996-03-19 1999-01-12 Apple Computer, Inc. Multicasting system for selecting a group of memory devices for operation
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Also Published As

Publication number Publication date
EP2251872A1 (en) 2010-11-17
ES2478274T3 (en) 2014-07-21
WO2009097693A1 (en) 2009-08-13
EP2251872B1 (en) 2014-04-09
US20090198857A1 (en) 2009-08-06
US8131913B2 (en) 2012-03-06

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