WO2009114680A2 - Cross-coupled transistor layouts in restricted gate level layout architecture - Google Patents
Cross-coupled transistor layouts in restricted gate level layout architecture Download PDFInfo
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- WO2009114680A2 WO2009114680A2 PCT/US2009/036937 US2009036937W WO2009114680A2 WO 2009114680 A2 WO2009114680 A2 WO 2009114680A2 US 2009036937 W US2009036937 W US 2009036937W WO 2009114680 A2 WO2009114680 A2 WO 2009114680A2
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Definitions
- a push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years.
- the chip area reduction provides an economic benefit for migrating to newer technologies.
- the 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%.
- the reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers.
- CMP chemical mechanical polishing
- An interference pattern occurs as each shape on the mask interacts with the light.
- the interference patterns from neighboring shapes can create constructive or destructive interference.
- unwanted shapes may be inadvertently created.
- desired shapes may be inadvertently removed.
- a particular shape is printed in a different manner than intended, possibly causing a device failure.
- Correction methodologies such as optical proximity correction (OPC), attempt to predict the impact from neighboring shapes and modify the mask such that the printed shape is fabricated as desired.
- OPC optical proximity correction
- a cross-coupled transistor configuration within a semiconductor chip includes a first P channel transistor having a first gate electrode defined in a gate level of the chip.
- the cross-coupled transistor configuration also includes a first N channel transistor having a second gate electrode defined in the gate level of the chip.
- the second gate electrode of the first N channel transistor is electrically connected to the first gate electrode of the first P channel transistor.
- the cross-coupled transistor configuration further includes a second P channel transistor having a third gate electrode defined in the gate level of the chip.
- the cross-coupled transistor configuration includes a second N channel transistor having a fourth gate electrode defined in the gate level of the chip.
- the fourth gate electrode of the second N channel transistor is electrically connected to the third gate electrode of the second P channel transistor.
- Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node.
- each of the first, second, third, and fourth gate electrodes corresponds to a portion of a respective gate level feature defined within a gate level feature layout channel.
- Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel.
- a cross-coupled transistor layout is disclosed.
- the cross- coupled transistor layout includes a first P channel transistor having a first gate electrode defined in a gate level of the chip.
- the cross-coupled transistor layout also includes a first N channel transistor having a second gate electrode defined in the gate level of the chip.
- the second gate electrode of the first N channel transistor is electrically connected to the first gate electrode of the first P channel transistor.
- the cross-coupled transistor layout further includes a second P channel transistor having a third gate electrode defined in the gate level of the chip.
- the cross-coupled transistor layout includes a second N channel transistor having a fourth gate electrode defined in the gate level of the chip.
- the fourth gate electrode of the second N channel transistor is electrically connected to the third gate electrode of the second P channel transistor.
- Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node.
- each of the first, second, third, and fourth gate electrodes corresponds to a portion of a respective gate level feature defined within a gate level feature layout channel.
- Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel.
- a semiconductor chip in another embodiment, includes a first P channel transistor defined by a corresponding gate electrode.
- the chip also includes a first N channel transistor defined by a corresponding gate electrode.
- the chip also includes a second P channel transistor defined by a corresponding gate electrode.
- the chip also includes a second N channel transistor defined by a corresponding gate electrode.
- Each of the gate electrodes of the first P channel, first N channel, second P channel, and second N channel transistors is defined within a gate level of the chip and is electrically connected to a common diffusion node.
- the gate electrode of the first P channel transistor is electrically connected to the gate electrode of the first N channel transistor.
- the gate electrode of the second P channel transistor is electrically connected to the gate electrode of the second N channel transistor.
- Each of the first, second, third, and fourth gate electrodes corresponds to a portion of a respective gate level feature defined within a gate level feature layout channel. Also, each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel.
- Figure IA shows an SRAM bit cell circuit, in accordance with the prior art
- Figure IB shows the SRAM bit cell of Figure IA with the inverters expanded to reveal their respective internal transistor configurations, in accordance with the prior art
- Figure 2 shows a cross-coupled transistor configuration, in accordance with one embodiment of the present invention
- Figure 3 A shows an example of gate electrode tracks defined within the restricted gate level layout architecture, in accordance with one embodiment of the present invention
- Figure 3B shows the exemplary restricted gate level layout architecture of Figure 3A with a number of exemplary gate level features defined therein, in accordance with one embodiment of the present invention
- Figure 4 shows diffusion and gate level layouts of a cross-coupled transistor configuration, in accordance with one embodiment of the present invention
- Figure 5 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on three gate electrode tracks with crossing gate electrode connections;
- Figure 6 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on four gate electrode tracks with crossing gate electrode connections;
- Figure 7 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on two gate electrode tracks without crossing gate electrode connections;
- Figure 8 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on three gate electrode tracks without crossing gate electrode connections
- Figure 9 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on four gate electrode tracks without crossing gate electrode connections
- Figure 10 shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention
- Figure 11 shows a multi-level layout including a cross-coupled transistor configuration defined on four gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention
- Figure 12 shows a multi-level layout including a cross-coupled transistor configuration defined on two gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention
- FIG. 14A with a detailed view of the pull up logic, and the pull down logic, in accordance with one embodiment of the present invention
- Figure 14C shows a multi-level layout of the multiplexer circuit of Figure 14B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention
- Figure 15A shows the multiplexer circuit of Figure 14A in which two cross- coupled transistors remain directly connected to the common node, and in which two cross-coupled transistors are positioned outside the pull up logic and pull down logic, respectively, relative to the common node, in accordance with one embodiment of the present invention
- Figure 15B shows an exemplary implementation of the multiplexer circuit of Figure 15A with a detailed view of the pull up logic and the pull down logic, in accordance with one embodiment of the present invention
- Figure 15C shows a multi-level layout of the multiplexer circuit of Figure 15B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention
- Figure 16A shows a generalized multiplexer circuit in which the cross-coupled transistors are connected to form two transmission gates to the common node, in accordance with one embodiment of the present invention
- Figure 16C shows a multi-level layout of the multiplexer circuit of Figure 16B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention
- Figure 17A shows a generalized multiplexer circuit in which two transistors of the four cross-coupled transistors are connected to form a transmission gate to the common node, in accordance with one embodiment of the present invention
- Figure 17B shows an exemplary implementation of the multiplexer circuit of
- Figure 18 A shows a generalized latch circuit implemented using the cross-coupled transistor configuration, in accordance with one embodiment of the present invention
- Figure 19B shows an exemplary implementation of the latch circuit of Figure 19A with a detailed view of the pull up driver logic, the pull down driver logic, the pull up feedback logic, and the pull down feedback logic, in accordance with one embodiment of the present invention
- Figure 21 A shows a generalized latch circuit in which cross-coupled transistors are connected to form two transmission gates to the common node, in accordance with one embodiment of the present invention
- Figure 22C shows a multi-level layout of the latch circuit of Figure 22B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- FIG. 1A shows an SRAM (Static Random Access Memory) bit cell circuit, in accordance with the prior art.
- the SRAM bit cell includes two cross-coupled inverters 106 and 102.
- an output 106B of inverter 106 is connected to an input 102 A of inverter 102, and an output 102B of inverter 102 is connected to an input 106A of inverter 106.
- the SRAM bit cell further includes two NMOS pass transistors 100 and 104.
- the NMOS pass transistor 100 is connected between a bit-line 103 and a node 109 corresponding to both the output 106B of inverter 106 and the input 102A of inverter 102.
- the NMOS pass transistor 104 is connected between a bit-line 105 and a node 111 corresponding to both the output 102B of inverter 102 and the input 106A of inverter 106.
- NMOS pass transistors 100 and 104 are each connected to a word line 107, which controls access to the SRAM bit cell through the NMOS pass transistors 100 and 104.
- the SRAM bit cell requires bi-directional write, which means that when bit-line 103 is driven high, bit-line 105 is driven low, vice- versa. It should be understood by those skilled in the art that a logic state stored in the SRAM bit cell is maintained in a complementary manner by nodes 109 and 111.
- FIG. IB shows the SRAM bit cell of Figure IA with the inverters 106 and 102 expanded to reveal their respective internal transistor configurations, in accordance with the prior art.
- the inverter 106 include a PMOS transistor 115 and an NMOS transistor 113.
- the respective gates of the PMOS and NMOS transistors 115, 113 are connected together to form the input 106A of inverter 106.
- each of PMOS and NMOS transistors 115, 113 have one of their respective terminals connected together to form the output 106B of inverter 106.
- a remaining terminal of PMOS transistor 115 is connected to a power supply 1 17.
- a remaining terminal of NMOS transistor 113 is connected to a ground potential 119.
- the inverter 102 is defined in an identical manner to inverter 106.
- the inverter 102 include a PMOS transistor 121 and an NMOS transistor 123.
- the respective gates of the PMOS and NMOS transistors 121, 123 are connected together to form the input 102 A of inverter 102.
- each of PMOS and NMOS transistors 121, 123 have one of their respective terminals connected together to form the output 102B of inverter 102.
- a remaining terminal of PMOS transistor 121 is connected to the power supply 117.
- a remaining terminal of NMOS transistor 123 is connected to the ground potential 119. Therefore, PMOS and NMOS transistors 121, 123 are activated in a complementary manner.
- the NMOS transistor 407 has one terminal connected to pull down logic 21 IB, and its other terminal connected to the common node 495. Respective gates of the PMOS transistor 401 and the NMOS transistor 407 are both connected to a gate node 491. Respective gates of the NMOS transistor 405 and the PMOS transistor 403 are both connected to a gate node 493.
- the gate nodes 491 and 493 are also referred to as control nodes 491 and 493, respectively.
- each of the common node 495, the gate node 491, and the gate node 493 can be referred to as an electrical connection 495, 491, 493, respectively.
- the cross-coupled transistor configuration includes four transistors: 1) a first PMOS transistor, 2) a first NMOS transistor, 3) a second PMOS transistor, and 4) a second NMOS transistor. Furthermore, the cross-coupled transistor configuration includes three required electrical connections: 1) each of the four transistors has one of its terminals connected to a same common node, 2) gates of one PMOS transistor and one NMOS transistor are both connected to a first gate node, and 3) gates of the other PMOS transistor and the other NMOS transistor are both connected to a second gate node.
- the SRAM bit cell of Figures 1A-1B does not include a cross-coupled transistor configuration.
- the cross- coupled "inverters" 106 and 102 within the SRAM bit cell neither represent nor infer a cross-coupled "transistor" configuration.
- the cross-coupled transistor configuration requires that each of the four transistors has one of its terminals electrically connected to the same common node. This does not occur in the SRAM bit cell.
- the terminals of PMOS transistor 115 and NMOS transistor 113 are connected together at node 109, but the terminals of PMOS transistor 121 and NMOS transistor 123 are connected together at node 111. More specifically, the terminals of PMOS transistor 115 and NMOS transistor 113 that are connected together at the output 106B of the inverter are connected to the gates of each of PMOS transistor 121 and NMOS transistor 123, and therefore are not connected to both of the terminals of PMOS transistor 121 and NMOS transistor 123. Therefore, the SRAM bit cell does not include four transistors (two PMOS and two NMOS) that each have one of its terminals connected together at a same common node. Consequently, the SRAM bit cell does represent or include a cross-coupled transistor configuration, such as described with regard to Figure 2.
- FIG. 3A shows an example of gate electrode tracks 301A-301E defined within the restricted gate level layout architecture, in accordance with one embodiment of the present invention.
- Gate electrode tracks 3O1A-3O1E are formed by parallel virtual lines that extend across the gate level layout of the chip, with a perpendicular spacing therebetween equal to a specified gate electrode pitch 307.
- complementary diffusion regions 303 and 305 are shown in Figure 3A. It should be understood that the diffusion regions 303 and 305 are defined in the diffusion level below the gate level. Also, it should be understood that the diffusion regions 303 and 305 are provided by way of example and in no way represent any limitation on diffusion region size, shape, and/or placement within the diffusion level relative to the restricted gate level layout architecture.
- a gate level feature layout channel is defined about a given gate electrode track so as to extend between gate electrode tracks adjacent to the given gate electrode track.
- gate level feature layout channels 301 A-I through 30 IE-I are defined about gate electrode tracks 30 IA through 30 IE, respectively.
- each gate electrode track has a corresponding gate level feature layout channel.
- the corresponding gate level feature layout channel extends as if there were a virtual gate electrode track outside the prescribed layout space, as illustrated by gate level feature layout channels 301 A-I and 301E-1.
- each gate level feature layout channel is defined to extend along an entire length of its corresponding gate electrode track.
- each gate level feature layout channel is defined to extend across the gate level layout within the portion of the chip to which the gate level layout is associated.
- gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with the given gate electrode track.
- a contiguous gate level feature can include both a portion which defines a gate electrode of a transistor, and a portion that does not define a gate electrode of a transistor.
- a contiguous gate level feature can extend over both a diffusion region and a dielectric region of an underlying chip level.
- each portion of a gate level feature that forms a gate electrode of a transistor is positioned to be substantially centered upon a given gate electrode track. Furthermore, in this embodiment, portions of the gate level feature that do not form a gate electrode of a transistor can be positioned within the gate level feature layout channel associated with the given gate electrode track. Therefore, a given gate level feature can be defined essentially anywhere within a given gate level feature layout channel, so long as gate electrode portions of the given gate level feature are centered upon the gate electrode track corresponding to the given gate level feature layout channel, and so long as the given gate level feature complies with design rule spacing requirements relative to other gate level features in adjacent gate level layout channels. Additionally, physical contact is prohibited between gate level features defined in gate level feature layout channels that are associated with adjacent gate electrode tracks.
- FIG. 3B shows the exemplary restricted gate level layout architecture of Figure 3A with a number of exemplary gate level features 309-323 defined therein, in accordance with one embodiment of the present invention.
- the gate level feature 309 is defined within the gate level feature layout channel 301A-1 associated with gate electrode track 301A.
- the gate electrode portions of gate level feature 309 are substantially centered upon the gate electrode track 301 A.
- the non-gate electrode portions of gate level feature 309 maintain design rule spacing requirements with gate level features 311 and 313 defined within adjacent gate level feature layout channel 301B-1.
- gate level features 311-323 are defined within their respective gate level feature layout channel, and have their gate electrode portions substantially centered upon the gate electrode track corresponding to their respective gate level feature layout channel.
- each of gate level features 311-323 maintains design rule spacing requirements with gate level features defined within adjacent gate level feature layout channels, and avoids physical contact with any another gate level feature defined within adjacent gate level feature layout channels.
- a gate electrode corresponds to a portion of a respective gate level feature that extends over a diffusion region, wherein the respective gate level feature is defined in its entirety within a gate level feature layout channel.
- Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel.
- each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary.
- a gate level of the various embodiments disclosed herein is defined as a restricted gate level, as discussed above. Some of the gate level features form gate electrodes of transistor devices. Others of the gate level features can form conductive segments extending between two points within the gate level. Also, others of the gate level features may be non-functional with respect to integrated circuit operation. It should be understood that the each of the gate level features, regardless of function, is defined to extend across the gate level within their respective gate level feature layout channels without physically contacting other gate level features defined with adjacent gate level feature layout channels.
- the gate level features are defined to provide a finite number of controlled layout shape-to-shape lithographic interactions which can be accurately predicted and optimized for in manufacturing and design processes.
- the gate level features are defined to avoid layout shape-to-shape spatial relationships which would introduce adverse lithographic interaction within the layout that cannot be accurately predicted and mitigated with high probability.
- changes in direction of gate level features within their gate level layout channels are acceptable when corresponding lithographic interactions are predictable and manageable.
- each of the gate level features regardless of function, is defined such that no gate level feature along a given gate electrode track is configured to connect directly within the gate level to another gate level feature defined along a different gate electrode track without utilizing a non-gate level feature.
- each connection between gate level features that are placed within different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, which may be defined in higher interconnect levels, i.e., through one or more interconnect levels above the gate level, or by way of local interconnect features at or below the gate level.
- the cross-coupled transistor configuration includes four transistors (2 PMOS transistors and 2 NMOS transistors).
- gate electrodes defined in accordance with the restricted gate level layout architecture are respectively used to form the four transistors of a cross-coupled transistor configuration layout.
- Figure 4 shows diffusion and gate level layouts of a cross- coupled transistor configuration, in accordance with one embodiment of the present invention.
- the cross-coupled transistor layout of Figure 4 includes the first PMOS transistor 401 defined by a gate electrode 401 A extending along a gate electrode track 450 and over a p-type diffusion region 480.
- the gate electrodes 40 IA and 407 A of the first PMOS transistor 401 and first NMOS transistor 407, respectively, are electrically connected to the first gate node 491 so as to be exposed to a substantially equivalent gate electrode voltage.
- the gate electrodes 403A and 405A of the second PMOS transistor 403 and second NMOS transistor 405, respectively, are electrically connected to the second gate node 493 so as to be exposed to a substantially equivalent gate electrode voltage.
- each of the four transistors 401, 403, 405, 407 has a respective diffusion terminal electrically connected to the common output node 495.
- the cross-coupled transistor layout can be implemented in a number of different ways within the restricted gate level layout architecture, hi the exemplary embodiment of Figure 4, the gate electrodes 401 A and 405A of the first PMOS transistor 401 and second NMOS transistor 405 are positioned along the same gate electrode track 450. Similarly, the gate electrodes 403A and 407A of the second PMOS transistor 403 and second NMOS transistor 407 are positioned along the same gate electrode track 456.
- the particular embodiment of Figure 4 can be characterized as a cross-coupled transistor configuration defined on two gate electrode tracks with crossing gate electrode connections.
- Figure 5 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on three gate electrode tracks with crossing gate electrode connections.
- the gate electrode 40 IA of the first PMOS transistor 401 is defined on the gate electrode track 450.
- the gate electrode 403A of the second PMOS transistor 403 is defined on the gate electrode track 456.
- the gate electrode 407A of the first NMOS transistor 407 is defined on a gate electrode track 456.
- the gate electrode 405A of the second NMOS transistor 405 is defined on a gate electrode track 448.
- the particular embodiment of Figure 5 can be characterized as a cross-coupled transistor configuration defined on three gate electrode tracks with crossing gate electrode connections.
- Figure 8 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on three gate electrode tracks without crossing gate electrode connections.
- the gate electrode 401 A of the first PMOS transistor 401 is defined on the gate electrode track 450.
- the gate electrode 407A of the first NMOS transistor 407 is also defined on a gate electrode track 450.
- the gate electrode 403A of the second PMOS transistor 403 is defined on the gate electrode track 454.
- the gate electrode 405 A of the second NMOS transistor 405 is defined on a gate electrode track 456.
- the particular embodiment of Figure 8 can be characterized as a cross-coupled transistor configuration defined on three gate electrode tracks without crossing gate electrode connections.
- Figure 9 shows a variation of the cross-coupled transistor configuration of Figure 4 in which the cross-coupled transistor configuration is defined on four gate electrode tracks without crossing gate electrode connections.
- the gate electrode 40 IA of the first PMOS transistor 401 is defined on the gate electrode track 450.
- the gate electrode 403 A of the second PMOS transistor 403 is defined on the gate electrode track 454.
- the gate electrode 407A of the first NMOS transistor 407 is defined on a gate electrode track 452.
- the gate electrode 405 A of the second NMOS transistor 405 is defined on a gate electrode track 456.
- the particular embodiment of Figure 9 can be characterized as a cross-coupled transistor configuration defined on four gate electrode tracks without crossing gate electrode connections.
- cross-coupled transistors 401, 403, 405, 407 of Figures 4-9 are depicted as having their own respective diffusion region 480, 482, 484, 486, respectively, other embodiments may utilize a contiguous p-type diffusion region for PMOS transistors 401 and 403, and/or utilize a contiguous n-type diffusion region for NMOS transistors 405 and 407.
- other embodiments may utilize a contiguous p-type diffusion region for PMOS transistors 401 and 403, and/or utilize a contiguous n-type diffusion region for NMOS transistors 405 and 407.
- the example layouts of Figures 4-9 depict the p-type diffusion regions 480 and 482 in a vertically aligned position, it should be understood that the p-type diffusion regions 480 and 482 may not be vertically aligned in other embodiments.
- Figures 4-9 depict the n- type diffusion regions 484 and 486 in a vertically aligned position, it should be understood that the n-type diffusion regions 484 and 486 may not be vertically aligned in other embodiments.
- the gate electrode connections are electrically represented by lines 491 and 493, and the common node electrical connection is represented by line 495.
- each of the gate electrode electrical connections 491, 493, and the common node electrical connection 495 can be structurally defined by a number of layout shapes extending through multiple chip levels.
- Figures 10-13 show examples of how the gate electrode electrical connections 491, 493, and the common node electrical connection 495 can be defined in different embodiments. It should be understood that the example layouts of Figures 10-13 are provided by way of example and in no way represent an exhaustive set of possible multi-level connections that can be utilized for the gate electrode electrical connections 491, 493, and the common node electrical connection
- Figure 11 shows a multi-level layout including a cross-coupled transistor configuration defined on four gate electrode tracks with crossing gate electrode connections, in accordance with one embodiment of the present invention.
- the layout of Figure 11 represents an exemplary implementation of the cross-coupled transistor embodiment of Figure 6.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407 A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1101, a (two- dimensional) metal- 1 structure 1103, and a gate contact 1105.
- the gate electrodes 403A and 405A of the second PMOS transistor 403 and second NMOS transistor 405, respectively, are formed by a contiguous gate level structure placed on the gate electrode track 456. Therefore, the electrical connection 493 between the gate electrodes 403 A and 405 A is made directly within the gate level along the single gate electrode track 456.
- the output node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1205, a (one-dimensional) metal-1 structure 1207, and a diffusion contact 1209.
- the corresponding cross- coupled transistor layout may include electrical connections between diffusion regions associated with the four cross-coupled transistors 401, 407, 403, 405, that cross in layout space without electrical communication therebetween.
- FIG. 13 shows a multi-level layout including a cross-coupled transistor configuration defined on three gate electrode tracks without crossing gate electrode connections, in accordance with one embodiment of the present invention.
- the layout of Figure 13 represents an exemplary implementation of the cross-coupled transistor embodiment of Figure 8.
- the gate electrodes 40 IA and 407 A of the first PMOS transistor 401 and first NMOS transistor 407, respectively, are formed by a contiguous gate level structure placed on the gate electrode track 450. Therefore, the electrical connection 491 between the gate electrodes 40 IA and 407 A is made directly within the gate level along the single gate electrode track 450.
- the electrical connection 493 between the gate electrode 403A of the second PMOS transistor 403 and the gate electrode 405A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1303, a (one-dimensional) metal- 1 structure 1305, and a gate contact 1307.
- the output node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1311, a (one-dimensional) metal- 1 structure 1313, and a diffusion contact 1315.
- electrical connection of the diffusion regions of the cross- coupled transistors to the common node 495 can be made using one or more local interconnect conductors defined at or below the gate level itself. This embodiment may also combine local interconnect conductors with conductors in higher levels (above the gate level) by way of contacts and/or vias to make the electrical connection of the diffusion regions of the cross-coupled transistors to the common node 495. Additionally, in various embodiments, conductive paths used to electrically connect the diffusion regions of the cross-coupled transistors to the common node 495 can be defined to traverse over essentially any area of the chip as required to accommodate a routing solution for the chip.
- diffusion regions are not restricted in size.
- any given diffusion region can be sized in an arbitrary manner as required to satisfy electrical and/or layout requirements.
- any given diffusion region can be shaped in an arbitrary manner as required to satisfy electrical and/or layout requirements.
- the four transistors of the cross-coupled transistor configuration as defined in accordance with the restricted gate level layout architecture, are not required to be the same size.
- the four transistors of the cross-coupled transistor configuration can either vary in size (transistor width or transistor gate length) or have the same size, depending on the applicable electrical and/or layout requirements.
- the four transistors of the cross-coupled transistor configuration are not required to be placed in close proximity to each, although they may be closely placed in some embodiments. More specifically, because connections between the transistors of the cross-coupled transistor configuration can be made by routing through as least one higher interconnect level, there is freedom in placement of the four transistors of the cross-coupled transistor configuration relative to each other. Although, it should be understood that a proximity of the four transistors of the cross- coupled transistor configuration may be governed in certain embodiments by electrical and/or layout optimization requirements.
- cross-coupled transistor configurations and corresponding layouts implemented using the restricted gate level layout architecture can be used to form many different electrical circuits.
- a portion of a modern semiconductor chip is likely to include a number of multiplexer circuits and/or latch circuits.
- Such multiplexer and/or latch circuits can be defined using cross-coupled transistor configurations and corresponding layouts based on the restricted gate level layout architecture, as disclosed herein.
- Example multiplexer embodiments implemented using the restricted gate level layout architecture and corresponding cross-coupled transistor configurations are described with regard to Figures 14A-17C.
- Example latch embodiments implemented using the restricted gate level layout architecture and corresponding cross-coupled transistor configurations are described with regard to Figures 18A-22C. It should be understood that the multiplexer and latch embodiments described with regard to Figures 14A-22C are provided by way of example and do not represent an exhaustive set of possible multiplexer and latch embodiments.
- Figure 14A shows a generalized multiplexer circuit in which all four cross-coupled transistors 401 , 405, 403, 407 are directly connected to the common node 495, in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- Pull up logic 1401 is electrically connected to the first PMOS transistor 401 at a terminal opposite the common node 495.
- Pull down logic 1403 is electrically connected to the second NMOS transistor 405 at a terminal opposite the common node 495.
- pull up logic 1405 is electrically connected to the second PMOS transistor 403 at a terminal opposite the common node 495.
- Pull down logic 1407 is electrically connected to the first NMOS transistor 407 at a terminal opposite the common node 495.
- FIG. 14B shows an exemplary implementation of the multiplexer circuit of Figure 14A with a detailed view of the pull up logic 1401 and 1405, and the pull down logic 1403 and 1407, in accordance with one embodiment of the present invention.
- the pull up logic 1401 is defined by a PMOS transistor 1401 A connected between a power supply (VDD) and a terminal 1411 of the first PMOS transistor 401 opposite the common node 495.
- the pull down logic 1403 is defined by an NMOS transistor 1403 A connected between a ground potential (GND) and a terminal 1413 of the second NMOS transistor 405 opposite the common node 495.
- Respective gates of the PMOS transistor 1401 A and NMOS transistor 1403 A are connected together at a node 1415.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1431, a (one-dimensional) metal-1 structure 1433, a via 1435, a (one-dimensional) metal-2 structure 1436, a via 1437, a (one-dimensional) metal-1 structure 1439, and a gate contact 1441.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1451, a (one-dimensional) metal-1 structure 1453, a via 1455, a (one-dimensional) metal-2 structure 1457, a via 1459, a (one-dimensional) metal-1 structure 1461, and a diffusion contact 1463.
- Respective gates of the PMOS transistor 1401A and NMOS transistor 1403A are connected to the node 1415 by a gate contact 1443.
- respective gates of the PMOS transistor 1405A and NMOS transistor 1407A are connected to the node 1421 by a gate contact 1465.
- Figure 15A shows the multiplexer circuit of Figure 14A in which the two cross- coupled transistors 401 and 405 remain directly connected to the common node 495, and in which the two cross-coupled transistors 403 and 407 are positioned outside the pull up logic 1405 and pull down logic 1407, respectively, relative to the common node 495, in accordance with one embodiment of the present invention.
- Pull up logic 1405 is electrically connected between the second PMOS transistor 403 and the common node 495.
- Pull down logic 1407 is electrically connected between the first NMOS transistor 407 and the common node 495.
- Figure 15A shows an exemplary implementation of the multiplexer circuit of Figure 15A with a detailed view of the pull up logic 1401 and 1405, and the pull down logic 1403 and 1407, in accordance with one embodiment of the present invention.
- the pull up logic 1401 is defined by the PMOS transistor 1401 A connected between VDD and the terminal 1411 of the first PMOS transistor 401 opposite the common node 495.
- the pull down logic 1403 is defined by NMOS transistor 1403A connected between GND and the terminal 1413 of the second NMOS transistor 405 opposite the common node 495. Respective gates of the PMOS transistor 140 IA and NMOS transistor 1403 A are connected together at the node 1415.
- the pull up logic 1405 is defined by the PMOS transistor 1405 A connected between the second PMOS transistor 403 and the common node 495.
- the pull down logic 1407 is defined by the NMOS transistor 1407 A connected between the first NMOS transistor 407 and the common node 495. Respective gates of the PMOS transistor 1405 A and NMOS transistor 1407 A are connected together at the node 1421. It should be understood that the implementations of pull up logic 1401, 1405 and pull down logic 1403, 1407 as shown in Figure 15B are exemplary. In other embodiments, logic different than that shown in Figure
- 15B can be used to implement the pull up logic 1401, 1405 and the pull down logic 1403, 1407.
- Figure 15C shows a multi-level layout of the multiplexer circuit of Figure 15B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1501, a (one-dimensional) metal-1 structure 1503, a via 1505, a (one-dimensional) metal-2 structure 1507, a via 1509, a (one-dimensional) metal-1 structure 1511, and a gate contact 1513.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405 A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1515, a (two-dimensional) metal-1 structure 1517, and a gate contact 1519.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1521, a (one-dimensional) metal-1 structure 1523, a via 1525, a (one- dimensional) metal-2 structure 1527, a via 1529, a (one-dimensional) metal-1 structure 1531, and a diffusion contact 1533.
- Figure 16A shows a generalized multiplexer circuit in which the cross-coupled transistors (401, 403, 405, 407) are connected to form two transmission gates 1602, 1604 to the common node 495, in accordance with one embodiment of the present invention.
- the cross-coupled transistors 401, 403, 405, 407
- gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- the first PMOS transistor 401 and second NMOS transistor 405 are connected to form a first transmission gate 1602 to the common node 495.
- the second PMOS transistor 403 and first NMOS transistor 407 are connected to form a second transmission gate 1604 to the common node 495.
- Driving logic 1601 is electrically connected to both the first PMOS transistor 401 and second NMOS transistor 405 at a terminal opposite the common node 495.
- Driving logic 1603 is electrically connected to both the second PMOS transistor 403 and first NMOS transistor 407 at a terminal opposite the common node 495.
- Figure 16B shows an exemplary implementation of the multiplexer circuit of Figure 16A with a detailed view of the driving logic 1601 and 1603, in accordance with one embodiment of the present invention.
- the driving logic 1601 is defined by an inverter 1601A and, the driving logic 1603 is defined by an inverter 1603 A.
- the driving logic 1601 and 1603 can be defined by any logic function, such as a two input NOR gate, a two input NAND gate, AND-OR logic, OR-AND logic, among others, by way of example.
- Figure 16C shows a multi-level layout of the multiplexer circuit of Figure 16B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1619, a (two-dimensional) metal- 1 structure 1621, and a gate contact 1623.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1605, a (one-dimensional) metal- 1 structure 1607, a via 1609, a (one-dimensional) metal-2 structure 1611, a via 1613, a (one-dimensional) metal- 1 structure 1615, and a gate contact 1617.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1625, a (one-dimensional) metal- 1 structure 1627, a via 1629, a (one-dimensional) metal-2 structure 1631, a via 1633, a (one-dimensional) metal-1 structure 1635, and a diffusion contact 1637.
- Transistors which form the inverter 1601A are shown within the region bounded by the dashed line 1601 AL.
- Transistors which form the inverter 1603 A are shown within the region bounded by the dashed line 1603AL.
- Figure 17A shows a generalized multiplexer circuit in which two transistors (403, 407) of the four cross-coupled transistors are connected to form a transmission gate 1702 to the common node 495, in accordance with one embodiment of the present invention.
- gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- the second PMOS transistor 403 and first NMOS transistor 407 are connected to form the transmission gate 1702 to the common node 495.
- Driving logic 1701 is electrically connected to both the second PMOS transistor 403 and first NMOS transistor 407 at a terminal opposite the common node 495.
- Pull up driving logic 1703 is electrically connected to the first PMOS transistor 401 at a terminal opposite the common node 495.
- pull down driving logic 1705 is electrically connected to the second NMOS transistor 405 at a terminal opposite the common node 495.
- FIG 17B shows an exemplary implementation of the multiplexer circuit of Figure 17A with a detailed view of the driving logic 1701, 1703, and 1705, in accordance with one embodiment of the present invention.
- the driving logic 1701 is defined by an inverter 170 IA.
- the pull up driving logic 1703 is defined by a PMOS transistor 1703 A connected between VDD and the first PMOS transistor 401.
- the pull down driving logic 1705 is defined by an NMOS transistor 1705 A connected between GND and the second NMOS transistor 405. Respective gates of the PMOS transistor 1703 A and NMOS transistor 1705 A are connected together at the node 1707. It should be understood that the implementations of driving logic 1701, 1703, and 1705, as shown in Figure 17B are exemplary. In other embodiments, logic different than that shown in Figure 17B can be used to implement the driving logic 1701, 1703, and 1705.
- Figure 17C shows a multi-level layout of the multiplexer circuit of Figure 17B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1723, a (two-dimensional) metal-1 structure 1725, and a gate contact 1727.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1709, a (one-dimensional) metal-1 structure 1711, a via 1713, a (one-dimensional) metal-2 structure 1715, a via 1717, a (one-dimensional) metal-1 structure 1719, and a gate contact 1721.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1729, a (one-dimensional) metal-1 structure 1731, a via 1733, a (one-dimensional) metal-2 structure 1735, a via 1737, a (one-dimensional) metal-1 structure 1739, and a diffusion contact 1741.
- Transistors which form the inverter 1701 A are shown within the region bounded by the dashed line 170 IAL.
- Respective gates of the PMOS transistor 1703 A and NMOS transistor 1705 A are connected to the node 1707 by a gate contact 1743.
- Figure 18A shows a generalized latch circuit implemented using the cross-coupled transistor configuration, in accordance with one embodiment of the present invention.
- the gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- the gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- Each of the four cross-coupled transistors are electrically connected to the common node 495. It should be understood that the common node 495 serves as a storage node in the latch circuit.
- Pull up driver logic 1805 is electrically connected to the second PMOS transistor 403 at a terminal opposite the common node 495.
- Pull down driver logic 1807 is electrically connected to the first NMOS transistor 407 at a terminal opposite the common node 495.
- Pull up feedback logic 1809 is electrically connected to the first PMOS transistor 401 at a terminal opposite the common node 495.
- Pull down feedback logic 1811 is electrically connected to the second NMOS transistor 405 at a terminal opposite the common node 495.
- the common node 495 is connected to an input of an inverter 1801.
- An output of the inverter 1801 is electrically connected to a feedback node 1803. It should be understood that in other embodiments the inverter 1801 can be replaced by any logic function, such as a two input NOR gate, a two input NAND gate, among others, or any complex logic function.
- the pull up feedback logic 1809 is defined by a PMOS transistor 1809A connected between VDD and the first PMOS transistor 401 opposite the common node 495.
- the pull down feedback logic 1811 is defined by an NMOS transistor 181 IA connected between GND and the second NMOS transistor 405 opposite the common node 495. Respective gates of the PMOS transistor 1809A and NMOS transistor 181 IA are connected together at the feedback node 1803. It should be understood that the implementations of pull up driver logic 1805, pull down driver logic 1807, pull up feedback logic 1809, and pull down feedback logic 1811 as shown in Figure
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1813, a (one-dimensional) metal- 1 structure 1815, a via 1817, a (one-dimensional) metal-2 structure 1819, a via 1821, a (one-dimensional) metal-1 structure 1823, and a gate contact 1825.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405 A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1827, a (two-dimensional) metal-1 structure 1829, and a gate contact 1831.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1833, a (one-dimensional) metal-1 structure 1835, a via 1837, a (one- dimensional) metal-2 structure 1839, a via 1841, a (two-dimensional) metal-1 structure 1843, and a diffusion contact 1845.
- Transistors which form the inverter 1801 are shown within the region bounded by the dashed line 180 IL.
- Figure 19B shows an exemplary implementation of the latch circuit of Figure 19A with a detailed view of the pull up driver logic 1805, pull down driver logic 1807, pull up feedback logic 1809, and pull down feedback logic 1811, in accordance with one embodiment of the present invention.
- the pull up feedback logic 1809 is defined by the PMOS transistor 1809A connected between VDD and the first PMOS transistor 401 opposite the common node 495.
- the pull down feedback logic 1811 is defined by NMOS transistor 181 IA connected between GND and the second NMOS transistor 405 opposite the common node 495. Respective gates of the PMOS transistor 1809 A and NMOS transistor 181 IA are connected together at the feedback node 1803.
- the electrical connection 491 between the gate electrode 401 A of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 1901, a (one-dimensional) metal- 1 structure 1903, a via 1905, a (one-dimensional) metal-2 structure 1907, a via 1909, a (one-dimensional) metal- 1 structure 1911, and a gate contact 1913.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405 A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 1915, a (two-dimensional) metal-1 structure 1917, and a gate contact 1919.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 1921, a (one-dimensional) metal-1 structure 1923, a via 1925, a (one- dimensional) metal-2 structure 1927, a via 1929, a (two-dimensional) metal-1 structure 1931, and a diffusion contact 1933.
- Transistors which form the inverter 1801 are shown within the region bounded by the dashed line 180 IL.
- Figure 2OA shows the latch circuit of Figure 18 A in which the two cross-coupled transistors 403 and 407 remain directly connected to the output node 495, and in which the two cross-coupled transistors 401 and 405 are positioned outside the pull up feedback logic 1809 and pull down feedback logic 181 1, respectively, relative to the common node 495, in accordance with one embodiment of the present invention.
- Pull up feedback logic 1809 is electrically connected between the first PMOS transistor 401 and the common node 495.
- Pull down feedback logic 181 1 is electrically connected between the second NMOS transistor 405 and the common node 495.
- Figure 2OA shows an exemplary implementation of the latch circuit of Figure 2OA with a detailed view of the pull up driver logic 1805, pull down driver logic 1807, pull up feedback logic 1809, and pull down feedback logic 1811, in accordance with one embodiment of the present invention.
- the pull up feedback logic 1809 is defined by the PMOS transistor 1809 A connected between the first PMOS transistor 401 and the common node 495.
- FIG. 2OB shows a multi-level layout of the latch circuit of Figure 2OB implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 2001, a (one-dimensional) metal- 1 structure 2003, a via 2005, a (one-dimensional) metal-2 structure 2007, a via 2009, a (one-dimensional) metal- 1 structure 2011, and a gate contact 2013.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405 A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 2015, a (one-dimensional) metal-1 structure 2017, and a gate contact 2019.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 2021, a (two-dimensional) metal-1 structure 2023, and a diffusion contact 2025. Transistors which form the inverter 1801 are shown within the region bounded by the dashed line 1801 L.
- Figure 21 A shows a generalized latch circuit in which the cross-coupled transistors (401, 403, 405, 407) are connected to form two transmission gates 2103, 2105 to the common node 495, in accordance with one embodiment of the present invention. As previously discussed, gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- the first PMOS transistor 401 and second NMOS transistor 405 are connected to form a first transmission gate 2103 to the common node 495.
- the second PMOS transistor 403 and first NMOS transistor 407 are connected to form a second transmission gate 2105 to the common node 495.
- Feedback logic 2109 is electrically connected to both the first PMOS transistor 401 and second NMOS transistor 405 at a terminal opposite the common node 495.
- Driving logic 2107 is electrically connected to both the second PMOS transistor 403 and first NMOS transistor 407 at a terminal opposite the common node 495.
- the common node 495 is connected to the input of the inverter 1801.
- the output of the inverter 1801 is electrically connected to a feedback node 2101. It should be understood that in other embodiments the inverter 1801 can be replaced by any logic function, such as a two input NOR gate, a two input NAND gate, among others, or any complex logic function.
- Figure 2 IB shows an exemplary implementation of the latch circuit of Figure 21 A with a detailed view of the driving logic 2107 and feedback logic 2109, in accordance with one embodiment of the present invention.
- the driving logic 2107 is defined by an inverter 2107 A.
- the feedback logic 2109 is defined by an inverter 2109A. It should be understood that in other embodiments, the driving logic 2107 and/or 2109 can be defined by logic other than an inverter.
- Figure 21C shows a multi-level layout of the latch circuit of Figure 21B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 401 A of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 2111, a (one-dimensional) metal-1 structure 2113, a via 21 15, a (one-dimensional) metal-2 structure 2117, a via 21 19, a (one-dimensional) metal-1 structure 2121, and a gate contact 2123.
- FIG. 22 A shows a generalized latch circuit in which two transistors (403, 407) of the four cross-coupled transistors are connected to form a transmission gate 2105 to the common node 495, in accordance with one embodiment of the present invention.
- gates of the first PMOS transistor 401 and first NMOS transistor 407 are electrically connected, as shown by electrical connection 491.
- gates of the second PMOS transistor 403 and second NMOS transistor 405 are electrically connected, as shown by electrical connection 493.
- the second PMOS transistor 403 and first NMOS transistor 407 are connected to form the transmission gate 2105 to the common node 495.
- Driving logic 2201 is electrically connected to both the second PMOS transistor 403 and first NMOS transistor 407 at a terminal opposite the common node 495.
- Pull up feedback logic 2203 is electrically connected to the first PMOS transistor 401 at a terminal opposite the common node 495.
- pull down feedback logic 2205 is electrically connected to the second NMOS transistor 405 at a terminal opposite the common node 495.
- Figure 22B shows an exemplary implementation of the latch circuit of Figure 22 A with a detailed view of the driving logic 2201, the pull up feedback logic 2203, and the pull down feedback logic 2205, in accordance with one embodiment of the present invention.
- the driving logic 2201 is defined by an inverter 220 IA.
- the pull up feedback logic 2203 is defined by a PMOS transistor 2203A connected between VDD and the first PMOS transistor 401.
- the pull down feedback logic 2205 is defined by an NMOS transistor 2205 A connected between GND and the second NMOS transistor 405. Respective gates of the PMOS transistor 2203A and NMOS transistor 2205A are connected together at the feedback node 2101. It should be understood that in other embodiments, the driving logic 2201 can be defined by logic other than an inverter. Also, it should be understood that in other embodiments, the pull up feedback logic 2203 and/or pull down feedback logic 2205 can be defined logic different than what is shown in Figure 22B.
- Figure 22C shows a multi-level layout of the latch circuit of Figure 22B implemented using a restricted gate level layout architecture cross-coupled transistor layout, in accordance with one embodiment of the present invention.
- the electrical connection 491 between the gate electrode 40 IA of the first PMOS transistor 401 and the gate electrode 407A of the first NMOS transistor 407 is formed by a multi-level connection that includes a gate contact 2207, a (one-dimensional) metal- 1 structure 2209, a via 2211, a (one-dimensional) metal-2 structure 2213, a via 2215, a (one-dimensional) metal- 1 structure 2217, and a gate contact 2219.
- the electrical connection 493 between the gate electrode 403 A of the second PMOS transistor 403 and the gate electrode 405 A of the second NMOS transistor 405 is formed by a multi-level connection that includes a gate contact 2221, a (two-dimensional) metal- 1 structure 2223, and a gate contact 2225.
- the common node electrical connection 495 is formed by a multi-level connection that includes a diffusion contact 2227, a (one-dimensional) metal-1 structure 2229, a via 2231, a (one- dimensional) metal-2 structure 2233, a via 2235, a (two-dimensional) metal-1 structure 2237, and a diffusion contact 2239.
- a cross-coupled transistor configuration is defined within a semiconductor chip. This embodiment is illustrated in part with regard to Figure 2.
- a first P channel transistor (401) is defined to include a first gate electrode (401A) defined in a gate level of the chip.
- a first N channel transistor (407) is defined to include a second gate electrode (407A) defined in the gate level of the chip.
- the second gate electrode (407A) of the first N channel transistor (407) is electrically connected to the first gate electrode (401A) of the first P channel transistor (401).
- a second P channel transistor (403) is defined to include a third gate electrode (403A) defined in the gate level of a chip.
- a second N channel transistor (405) is defined to include a fourth gate electrode (405A) defined in the gate level of the chip.
- the fourth gate electrode (405 A) of the second N channel transistor (405) is electrically connected to the third gate electrode (403A) of the second P channel transistor (403).
- each of the first P channel transistor (401), first N channel transistor (407), second P channel transistor (403), and second N channel transistor (405) has a respective diffusion terminal electrically connected to a common node (495).
- each of the first (401A), second (407A), third (403A), and fourth (405 A) gate electrodes is defined to extend along any of a number of gate electrode tracks, such as described with regard to Figure 3.
- the number of gate electrode tracks extend across the gate level of the chip in a parallel orientation with respect to each other.
- each of the first (401A), second (407A), third (403A), and fourth (405A) gate electrodes corresponds to a portion of a respective gate level feature defined within a gate level feature layout channel.
- Each gate level feature is defined within its gate level feature layout channel without physically contacting another gate level feature defined within an adjoining gate level feature layout channel.
- Each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary, such as described with regard to Figure 3B.
- both the second gate electrode (407A) and the first gate electrode (401A) are formed from a single gate level feature that is defined within a same gate level feature layout channel that extends along a single gate electrode track over both a p type diffusion region and an n type diffusion region.
- the fourth gate electrode (405A) is electrically connected to the third gate electrode (403A) through at least one electrical conductor defined within any chip level other than the gate level.
- both the second gate electrode (407A) and the first gate electrode (401 A) are formed from a first gate level feature that is defined within a first gate level feature layout channel that extends along a first gate electrode track over both a p type diffusion region and an n type diffusion region.
- both the fourth gate electrode (405A) and the third gate electrode (403 A) are formed from a second gate level feature that is defined within a second gate level feature layout channel that extends along a second gate electrode track over both a p type diffusion region and an n type diffusion region.
- the first configuration of pull-up logic (1401) is defined by a third P channel transistor (1401A), and the second configuration of pull-down logic (1403) is defined by a third N channel transistor (1403A). Respective gates of the third P channel transistor (1401A) and third N channel transistor (1403A) are electrically connected together so as to receive a substantially equivalent electrical signal.
- the first configuration of pull-down logic (1407) is defined by a fourth N channel transistor (1407A)
- the second configuration of pull-up logic (1405) is defined by a fourth P channel transistor (1405A).
- Respective gates of the fourth P channel transistor (1405A) and fourth N channel transistor (1407A) are electrically connected together so as to receive a substantially equivalent electrical signal.
- the above-described gate electrode cross-coupled transistor configuration is used to implement a multiplexer having one transmission gate. This embodiment is illustrated in part with regard to Figure 17.
- a first configuration of pull-up logic (1703) is electrically connected to the first P channel transistor (401)
- a first configuration of pull-down logic (1705) electrically connected to the second N channel transistor (405)
- mux driving logic (1701) is electrically connected to both the second P channel transistor (403) and the first N channel transistor (407).
- the first configuration of pull-up logic (1703) is defined by a third P channel transistor (1703A)
- the first configuration of pull-down logic (1705) is defined by a third N channel transistor (1705A).
- Respective gates of the third P channel transistor (1703A) and third N channel transistor (1705A) are electrically connected together so as to receive a substantially equivalent electrical signal.
- the mux driving logic (1701) is defined by an inverter (1701 A).
- the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having no transmission gates. This embodiment is illustrated in part with regard to Figures 18-20.
- pull-up driver logic (1805) is electrically connected to the second P channel transistor (403)
- pull-down driver logic (1807) is electrically connected to the first N channel transistor (407)
- pull-up feedback logic (1809) is electrically connected to the first P channel transistor (401)
- pull-down feedback logic (1811) is electrically connected to the second N channel transistor (405).
- the latch includes an inverter (1801) having an input connected to the common node (495) and an output connected to a feedback node (1803).
- Each of the pull-up feedback logic (1809) and pull-down feedback logic (1811) is connected to the feedback node (1803).
- the above-described gate electrode cross-coupled transistor configuration is used to implement a latch having two transmission gates.
- driving logic (2107) is electrically connected to both the second P channel transistor (403) and the first N channel transistor (407).
- feedback logic (2109) is electrically connected to both the first P channel transistor (401) and the second N channel transistor (405).
- the latch further includes a first inverter (1801) having an input connected to the common node (495) and an output connected to a feedback node (2101).
- the feedback logic (2109) is electrically connected to the feedback node (2101).
- the driving logic (2107) is defined by a second inverter (2107A)
- the feedback logic (2109) is defined by a third inverter (2109A).
- the computer readable medium can also be distributed over a network of coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.
- Any of the operations described herein that form part of the invention are useful machine operations.
- the invention also relates to a device or an apparatus for performing these operations.
- the apparatus may be specially constructed for the required purpose, such as a special purpose computer.
- the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.
- the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network.
- the embodiments of the present invention can also be defined as a machine that transforms data from one state to another state.
- the data may represent an article, that can be represented as an electronic signal and electronically manipulate data.
- the transformed data can, in some cases, be visually depicted on a display, representing the physical object that results from the transformation of data.
- the transformed data can be saved to storage generally, or in particular formats that enable the construction or depiction of a physical and tangible object.
- the manipulation can be performed by a processor. In such an example, the processor thus transforms the data from one thing to another.
- the methods can be processed by one or more machines or processors that can be connected over a network.
- Each machine can transform data from one state or thing to another, and can also process data, save data to storage, transmit data over a network, display the result, or communicate the result to another machine.
Abstract
Description
Claims
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JP2010550861A JP5628050B2 (en) | 2008-03-13 | 2009-03-12 | Cross-coupled transistor layout in constrained gate level layout architecture |
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US12/402,465 US7956421B2 (en) | 2008-03-13 | 2009-03-11 | Cross-coupled transistor layouts in restricted gate level layout architecture |
US12/402,465 | 2009-03-11 |
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