WO2010027579A3 - Approximate functional matching in electronic systems - Google Patents
Approximate functional matching in electronic systems Download PDFInfo
- Publication number
- WO2010027579A3 WO2010027579A3 PCT/US2009/051770 US2009051770W WO2010027579A3 WO 2010027579 A3 WO2010027579 A3 WO 2010027579A3 US 2009051770 W US2009051770 W US 2009051770W WO 2010027579 A3 WO2010027579 A3 WO 2010027579A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- functional matching
- electronic systems
- approximate functional
- matching
- subsets
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/204,777 | 2008-09-04 | ||
US12/204,777 US8453084B2 (en) | 2008-09-04 | 2008-09-04 | Approximate functional matching in electronic systems |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010027579A2 WO2010027579A2 (en) | 2010-03-11 |
WO2010027579A3 true WO2010027579A3 (en) | 2010-05-14 |
Family
ID=41727199
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/051770 WO2010027579A2 (en) | 2008-09-04 | 2009-07-24 | Approximate functional matching in electronic systems |
Country Status (3)
Country | Link |
---|---|
US (3) | US8453084B2 (en) |
TW (1) | TWI484362B (en) |
WO (1) | WO2010027579A2 (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8453084B2 (en) | 2008-09-04 | 2013-05-28 | Synopsys, Inc. | Approximate functional matching in electronic systems |
US8141024B2 (en) | 2008-09-04 | 2012-03-20 | Synopsys, Inc. | Temporally-assisted resource sharing in electronic systems |
US10713069B2 (en) | 2008-09-04 | 2020-07-14 | Synopsys, Inc. | Software and hardware emulation system |
US8635579B1 (en) | 2012-12-31 | 2014-01-21 | Synopsys, Inc. | Local clock skew optimization |
WO2014145965A1 (en) * | 2013-03-15 | 2014-09-18 | Locus Analytics, Llc | Domain-specific syntax tagging in a functional information system |
US9811503B1 (en) | 2015-01-28 | 2017-11-07 | Altera Corporation | Methods for implementing arithmetic functions with user-defined input and output formats |
WO2017019883A1 (en) * | 2015-07-30 | 2017-02-02 | Algebraix Data Corp. | Locality-sensitive hashing for algebraic expressions |
US9875330B2 (en) | 2015-12-04 | 2018-01-23 | Xilinx, Inc. | Folding duplicate instances of modules in a circuit design |
CN108920183B (en) * | 2018-05-31 | 2022-11-18 | 创新先进技术有限公司 | Service decision method, device and equipment |
CN110647666B (en) * | 2019-09-03 | 2023-12-19 | 平安科技(深圳)有限公司 | Intelligent matching method and device for templates and formulas and computer readable storage medium |
US11055463B1 (en) * | 2020-04-01 | 2021-07-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Systems and methods for gate array with partial common inputs |
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US6957412B1 (en) * | 2002-11-15 | 2005-10-18 | Altera Corporation | Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements |
US20080155508A1 (en) * | 2006-12-13 | 2008-06-26 | Infosys Technologies Ltd. | Evaluating programmer efficiency in maintaining software systems |
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US6020760A (en) | 1997-07-16 | 2000-02-01 | Altera Corporation | I/O buffer circuit with pin multiplexing |
US6401176B1 (en) | 1997-11-14 | 2002-06-04 | Agere Systems Guardian Corp. | Multiple agent use of a multi-ported shared memory |
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US6735712B1 (en) | 2000-09-08 | 2004-05-11 | Intel Corporation | Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains |
US6560761B1 (en) | 2001-03-29 | 2003-05-06 | Lsi Logic Corporation | Method of datapath cell placement for bitwise and non-bitwise integrated circuit designs |
US6438730B1 (en) | 2001-05-30 | 2002-08-20 | Lsi Logic Corporation | RTL code optimization for resource sharing structures |
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US8453084B2 (en) | 2008-09-04 | 2013-05-28 | Synopsys, Inc. | Approximate functional matching in electronic systems |
US8141024B2 (en) | 2008-09-04 | 2012-03-20 | Synopsys, Inc. | Temporally-assisted resource sharing in electronic systems |
-
2008
- 2008-09-04 US US12/204,777 patent/US8453084B2/en active Active
-
2009
- 2009-07-24 WO PCT/US2009/051770 patent/WO2010027579A2/en active Application Filing
- 2009-07-30 TW TW098125727A patent/TWI484362B/en active
-
2013
- 2013-05-23 US US13/901,462 patent/US9285796B2/en active Active
-
2016
- 2016-03-14 US US15/069,841 patent/US20160196133A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5606564A (en) * | 1995-05-19 | 1997-02-25 | Cirrus Logic Inc. | Test logic circuit and method for verifying internal logic of an integrated circuit |
US20020109682A1 (en) * | 2001-02-09 | 2002-08-15 | Intrinsic Graphics, Inc. | Method, system and computer program product for efficiently utilizing limited resources in a graphics device |
US6957412B1 (en) * | 2002-11-15 | 2005-10-18 | Altera Corporation | Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements |
US20080155508A1 (en) * | 2006-12-13 | 2008-06-26 | Infosys Technologies Ltd. | Evaluating programmer efficiency in maintaining software systems |
Non-Patent Citations (4)
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CHOI ET AL.: "Fast Logic Minimization Algorithm for Programmable-Logic-Array Design", JOURNAL OF THE KOREAN INSTITUTE OF ELECTRONICS ENGINEERS, vol. 22, no. 2, 1985, pages 25 - 30 * |
CORAZAO ET AL.: "Performance Optimization Using Template Mapping for Datapath- Intensive High-Level Synthesis", IEEE TRAN. ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 15, no. 8, August 1996 (1996-08-01), pages 877 - 888 * |
ZARETSKY ET AL.: "Dynamic template generation for resource sharing in control and data flow graphs", VLSI DESIGN, 2006. CONFERENCE ON EMBEDDED SYSTEMS AND DESIGN, - January 2006 (2006-01-01) * |
Also Published As
Publication number | Publication date |
---|---|
US8453084B2 (en) | 2013-05-28 |
WO2010027579A2 (en) | 2010-03-11 |
US9285796B2 (en) | 2016-03-15 |
TW201011585A (en) | 2010-03-16 |
US20130254430A1 (en) | 2013-09-26 |
TWI484362B (en) | 2015-05-11 |
US20100058298A1 (en) | 2010-03-04 |
US20160196133A1 (en) | 2016-07-07 |
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