WO2011046895A3 - Interrupt masking for multi-core processors - Google Patents

Interrupt masking for multi-core processors Download PDF

Info

Publication number
WO2011046895A3
WO2011046895A3 PCT/US2010/052244 US2010052244W WO2011046895A3 WO 2011046895 A3 WO2011046895 A3 WO 2011046895A3 US 2010052244 W US2010052244 W US 2010052244W WO 2011046895 A3 WO2011046895 A3 WO 2011046895A3
Authority
WO
WIPO (PCT)
Prior art keywords
cim
interrupt
core
core processors
interrupt masking
Prior art date
Application number
PCT/US2010/052244
Other languages
French (fr)
Other versions
WO2011046895A2 (en
Inventor
Ezekiel John Joseph Kruglick
Original Assignee
Empire Technology Development Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Development Llc filed Critical Empire Technology Development Llc
Priority to JP2012534273A priority Critical patent/JP5492305B2/en
Priority to EP10823917.9A priority patent/EP2488953B1/en
Publication of WO2011046895A2 publication Critical patent/WO2011046895A2/en
Publication of WO2011046895A3 publication Critical patent/WO2011046895A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask ("CIM") can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine ("ISR") that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.
PCT/US2010/052244 2009-10-13 2010-10-12 Interrupt masking for multi-core processors WO2011046895A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012534273A JP5492305B2 (en) 2009-10-13 2010-10-12 Interrupt mask for multi-core processors
EP10823917.9A EP2488953B1 (en) 2009-10-13 2010-10-12 Interrupt masking for multi-core processors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/578,270 US8234431B2 (en) 2009-10-13 2009-10-13 Interrupt masking for multi-core processors
US12/578,270 2009-10-13

Publications (2)

Publication Number Publication Date
WO2011046895A2 WO2011046895A2 (en) 2011-04-21
WO2011046895A3 true WO2011046895A3 (en) 2012-04-05

Family

ID=43855723

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/052244 WO2011046895A2 (en) 2009-10-13 2010-10-12 Interrupt masking for multi-core processors

Country Status (4)

Country Link
US (1) US8234431B2 (en)
EP (1) EP2488953B1 (en)
JP (1) JP5492305B2 (en)
WO (1) WO2011046895A2 (en)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2166457B1 (en) * 2008-09-12 2014-04-23 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Interrupt controller and methods of operation
US8321614B2 (en) * 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
WO2011044398A2 (en) * 2009-10-07 2011-04-14 Qsigma, Inc. Computer for amdahl-compliant algorithms like matrix inversion
US8321615B2 (en) * 2009-12-18 2012-11-27 Intel Corporation Source core interrupt steering
KR101717494B1 (en) * 2010-10-08 2017-03-28 삼성전자주식회사 Apparatus and Method for processing interrupt
EP2681656B1 (en) * 2011-05-17 2017-01-18 Siemens Aktiengesellschaft Multicore host-system mit einer echzeit-erweiterung und verfahren zum betreiben eines solchen host-systems
KR101867336B1 (en) * 2011-07-11 2018-06-15 삼성전자주식회사 Apparatus and method for generating interrupt which supports multi processors
KR20130021637A (en) * 2011-08-23 2013-03-06 삼성전자주식회사 Method and apparatus for interrupt allocation of multi-core system
KR102082242B1 (en) 2011-09-06 2020-02-27 인텔 코포레이션 Power efficient processor architecture
US8972642B2 (en) * 2011-10-04 2015-03-03 Qualcomm Incorporated Low latency two-level interrupt controller interface to multi-threaded processor
TWI463406B (en) * 2011-10-31 2014-12-01 Univ Nat Taiwan Real-time interrupt handling system with preempt function and method thereof
US9250682B2 (en) 2012-12-31 2016-02-02 Intel Corporation Distributed power management for multi-core processors
US9164935B2 (en) 2013-01-04 2015-10-20 International Business Machines Corporation Determining when to throttle interrupts to limit interrupt processing to an interrupt processing time period
KR102082859B1 (en) * 2013-01-07 2020-02-28 삼성전자주식회사 System on chip including a plurality of heterogeneous cores and operating method therof
US9524195B2 (en) 2014-02-27 2016-12-20 International Business Machines Corporation Adaptive process for data sharing with selection of lock elision and locking
WO2015073009A1 (en) * 2013-11-14 2015-05-21 Hewlett-Packard Development Company, L.P. Mark cache entry
US9412063B2 (en) 2013-12-27 2016-08-09 International Business Machines Corporation Transform architecture for multiple neurosynaptic core circuits
US9406015B2 (en) 2013-12-27 2016-08-02 International Business Machines Corporation Transform for a neurosynaptic core circuit
US9336097B2 (en) 2014-02-27 2016-05-10 International Business Machines Corporation Salvaging hardware transactions
US9430273B2 (en) 2014-02-27 2016-08-30 International Business Machines Corporation Suppressing aborting a transaction beyond a threshold execution duration based on the predicted duration
US9262206B2 (en) 2014-02-27 2016-02-16 International Business Machines Corporation Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments
US20150242216A1 (en) 2014-02-27 2015-08-27 International Business Machines Corporation Committing hardware transactions that are about to run out of resource
US9471371B2 (en) 2014-02-27 2016-10-18 International Business Machines Corporation Dynamic prediction of concurrent hardware transactions resource requirements and allocation
US9424072B2 (en) 2014-02-27 2016-08-23 International Business Machines Corporation Alerting hardware transactions that are about to run out of space
US9329946B2 (en) 2014-02-27 2016-05-03 International Business Machines Corporation Salvaging hardware transactions
US9442853B2 (en) 2014-02-27 2016-09-13 International Business Machines Corporation Salvaging lock elision transactions with instructions to change execution type
US9311178B2 (en) 2014-02-27 2016-04-12 International Business Machines Corporation Salvaging hardware transactions with instructions
US9411729B2 (en) 2014-02-27 2016-08-09 International Business Machines Corporation Salvaging lock elision transactions
US9361041B2 (en) 2014-02-27 2016-06-07 International Business Machines Corporation Hint instruction for managing transactional aborts in transactional memory computing environments
US9442775B2 (en) 2014-02-27 2016-09-13 International Business Machines Corporation Salvaging hardware transactions with instructions to transfer transaction execution control
US9645879B2 (en) 2014-02-27 2017-05-09 International Business Machines Corporation Salvaging hardware transactions with instructions
US9465673B2 (en) 2014-02-27 2016-10-11 International Business Machines Corporation Deferral instruction for managing transactional aborts in transactional memory computing environments to complete transaction by deferring disruptive events handling
US9575890B2 (en) 2014-02-27 2017-02-21 International Business Machines Corporation Supporting atomic accumulation with an addressable accumulator
US9524187B2 (en) 2014-03-02 2016-12-20 International Business Machines Corporation Executing instruction with threshold indicating nearing of completion of transaction
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
US20160188503A1 (en) * 2014-12-25 2016-06-30 Intel Corporation Virtual legacy wire
US10768984B2 (en) 2015-06-11 2020-09-08 Honeywell International Inc. Systems and methods for scheduling tasks using sliding time windows
US10013279B2 (en) 2015-07-28 2018-07-03 International Business Machines Corporation Processing interrupt requests
US9747139B1 (en) * 2016-10-19 2017-08-29 International Business Machines Corporation Performance-based multi-mode task dispatching in a multi-processor core system for high temperature avoidance
US10719902B2 (en) * 2017-04-17 2020-07-21 Intel Corporation Thread serialization, distributed parallel programming, and runtime extensions of parallel computing platform
US11126474B1 (en) * 2017-06-14 2021-09-21 Amazon Technologies, Inc. Reducing resource lock time for a virtual processing unit
US10802831B2 (en) * 2017-06-30 2020-10-13 Sap Se Managing parallel processing
US10592281B1 (en) 2017-09-28 2020-03-17 Amazon Technologies, Inc. Wait optimizer for recording an order of first entry into a wait mode by a virtual central processing unit
US10423550B2 (en) * 2017-10-25 2019-09-24 International Business Machines Corporation Managing efficient selection of a particular processor thread for handling an interrupt
US10276251B1 (en) * 2017-12-21 2019-04-30 Sandisk Technologies Llc Partial memory die with masked verify
CN110119304B (en) * 2018-02-07 2021-08-31 华为技术有限公司 Interrupt processing method and device and server
EP4038535A1 (en) * 2019-10-23 2022-08-10 Huawei Technologies Co., Ltd. Secure peripheral component access
CN111209240B (en) * 2019-12-23 2021-08-03 深圳优地科技有限公司 Data transmission method, electronic equipment and storage medium
KR20220094601A (en) 2020-12-29 2022-07-06 삼성전자주식회사 Storage device and method for operating the device
DE102022109559A1 (en) 2022-04-20 2023-10-26 Infineon Technologies Ag Processing interrupts

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050010707A1 (en) * 2003-07-07 2005-01-13 Arm Limited Data processing apparatus and method for handling interrupts
US20060026322A1 (en) * 2004-07-27 2006-02-02 Texas Instruments Incorporated Interrupt management in dual core processors

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5110742A (en) * 1974-07-17 1976-01-28 Hitachi Ltd
US4047161A (en) * 1976-04-30 1977-09-06 International Business Machines Corporation Task management apparatus
NL7907179A (en) * 1979-09-27 1981-03-31 Philips Nv SIGNAL PROCESSOR DEVICE WITH CONDITIONAL INTERRUPT UNIT AND MULTIPROCESSOR SYSTEM WITH THESE SIGNAL PROCESSOR DEVICES.
US4964040A (en) * 1983-01-03 1990-10-16 United States Of America As Represented By The Secretary Of The Navy Computer hardware executive
US4779194A (en) * 1985-10-15 1988-10-18 Unisys Corporation Event allocation mechanism for a large data processing system
JPS63184860A (en) * 1987-01-27 1988-07-30 Fuji Electric Co Ltd Interruption request control system for multiprocessor system
US5065310A (en) * 1989-05-10 1991-11-12 International Business Machines Corporation Reducing cache-reload transient at a context swap
JP2831083B2 (en) * 1990-03-08 1998-12-02 株式会社日立製作所 Multiprocessor system and interrupt controller
US5179707A (en) * 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
US5452452A (en) * 1990-06-11 1995-09-19 Cray Research, Inc. System having integrated dispatcher for self scheduling processors to execute multiple types of processes
US5613128A (en) * 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
US5555420A (en) * 1990-12-21 1996-09-10 Intel Corporation Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management
US5495615A (en) 1990-12-21 1996-02-27 Intel Corp Multiprocessor interrupt controller with remote reading of interrupt control registers
JP2855298B2 (en) * 1990-12-21 1999-02-10 インテル・コーポレーション Arbitration method of interrupt request and multiprocessor system
US5410710A (en) * 1990-12-21 1995-04-25 Intel Corporation Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
US6714559B1 (en) * 1991-12-04 2004-03-30 Broadcom Corporation Redundant radio frequency network having a roaming terminal communication protocol
JPH0528114A (en) * 1991-07-23 1993-02-05 Yokogawa Electric Corp Multiprocessor system
US5371872A (en) * 1991-10-28 1994-12-06 International Business Machines Corporation Method and apparatus for controlling operation of a cache memory during an interrupt
US5313584A (en) * 1991-11-25 1994-05-17 Unisys Corporation Multiple I/O processor system
JPH05324569A (en) * 1992-05-21 1993-12-07 Mitsubishi Electric Corp Interruption control system
EP0602858A1 (en) 1992-12-18 1994-06-22 International Business Machines Corporation Apparatus and method for servicing interrupts in a multiprocessor system
US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
SG48803A1 (en) * 1993-04-19 1998-05-18 Intel Corp Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
JPH0721045A (en) * 1993-06-15 1995-01-24 Sony Corp Information processing system
US5442758A (en) * 1993-07-19 1995-08-15 Sequent Computer Systems, Inc. Apparatus and method for achieving reduced overhead mutual exclusion and maintaining coherency in a multiprocessor system utilizing execution history and thread monitoring
JPH07114479A (en) * 1993-10-19 1995-05-02 Hitachi Ltd Interruption control system
JPH07160656A (en) * 1993-12-13 1995-06-23 Nippon Telegr & Teleph Corp <Ntt> External interruption control method
US5564060A (en) * 1994-05-31 1996-10-08 Advanced Micro Devices Interrupt handling mechanism to prevent spurious interrupts in a symmetrical multiprocessing system
EP0685798B1 (en) 1994-05-31 2003-07-16 Advanced Micro Devices, Inc. Interrupt controllers in symmetrical multiprocessing systems
US5646676A (en) * 1995-05-30 1997-07-08 International Business Machines Corporation Scalable interactive multimedia server system for providing on demand data
US5944809A (en) 1996-08-20 1999-08-31 Compaq Computer Corporation Method and apparatus for distributing interrupts in a symmetric multiprocessor system
US5918057A (en) * 1997-03-20 1999-06-29 Industrial Technology Research Institute Method and apparatus for dispatching multiple interrupt requests simultaneously
US5905897A (en) * 1997-03-20 1999-05-18 Industrial Technology Research Institute Method and apparatus for selecting a nonblocked interrupt request
US5889978A (en) * 1997-04-18 1999-03-30 Intel Corporation Emulation of interrupt control mechanism in a multiprocessor system
JPH11338833A (en) * 1998-05-22 1999-12-10 Hitachi Ltd Multiprocessor type controller and scalable controller system
JP2000029719A (en) 1998-07-14 2000-01-28 Nippon Signal Co Ltd:The Interrupt controller
US6189065B1 (en) * 1998-09-28 2001-02-13 International Business Machines Corporation Method and apparatus for interrupt load balancing for powerPC processors
GB2343269A (en) * 1998-10-30 2000-05-03 Ericsson Telefon Ab L M Processing arrangements
US6148361A (en) * 1998-12-17 2000-11-14 International Business Machines Corporation Interrupt architecture for a non-uniform memory access (NUMA) data processing system
US6418497B1 (en) * 1998-12-21 2002-07-09 International Business Machines Corporation Method and system for interrupt handling using system pipelined packet transfers
US6205508B1 (en) * 1999-02-16 2001-03-20 Advanced Micro Devices, Inc. Method for distributing interrupts in a multi-processor system
JP2001005676A (en) * 1999-06-18 2001-01-12 Mitsubishi Electric Corp Interruption processor
US20040100982A1 (en) * 1999-09-30 2004-05-27 Sivaram Balasubramanian Distributed real-time operating system
JP2001290660A (en) 2000-04-10 2001-10-19 Mitsubishi Electric Corp Interrupt factor selector
US6983339B1 (en) * 2000-09-29 2006-01-03 Intel Corporation Method and apparatus for processing interrupts of a bus
US7747757B2 (en) * 2000-11-17 2010-06-29 Computer Associates Think, Inc. Distributed network query
US20020087775A1 (en) * 2000-12-29 2002-07-04 Looi Lily P. Apparatus and method for interrupt delivery
JP3861625B2 (en) * 2001-06-13 2006-12-20 ソニー株式会社 Data transfer system, data transfer device, recording device, and data transfer method
US6779065B2 (en) * 2001-08-31 2004-08-17 Intel Corporation Mechanism for interrupt handling in computer systems that support concurrent execution of multiple threads
US6996745B1 (en) * 2001-09-27 2006-02-07 Sun Microsystems, Inc. Process for shutting down a CPU in a SMP configuration
US7328294B2 (en) * 2001-12-03 2008-02-05 Sun Microsystems, Inc. Methods and apparatus for distributing interrupts
US7039740B2 (en) * 2002-07-19 2006-05-02 Newisys, Inc. Interrupt handling in systems having multiple multi-processor clusters
US7461215B2 (en) * 2002-10-08 2008-12-02 Rmi Corporation Advanced processor with implementation of memory ordering on a ring based data movement network
US7191349B2 (en) 2002-12-26 2007-03-13 Intel Corporation Mechanism for processor power state aware distribution of lowest priority interrupt
US7350005B2 (en) * 2003-05-23 2008-03-25 Arm Limited Handling interrupts in a system having multiple data processing units
US7117285B2 (en) * 2003-08-29 2006-10-03 Sun Microsystems, Inc. Method and system for efficiently directing interrupts
US7003611B2 (en) * 2003-09-30 2006-02-21 International Business Machines Corporation Method and apparatus for handling interrupts using a set of interrupts servers associated with presentation controllers
US7594234B1 (en) * 2004-06-04 2009-09-22 Sun Microsystems, Inc. Adaptive spin-then-block mutual exclusion in multi-threaded processing
JP2006243865A (en) * 2005-03-01 2006-09-14 Seiko Epson Corp Processor and information processing method
US7581052B1 (en) * 2005-08-22 2009-08-25 Sun Microsystems, Inc. Approach for distributing multiple interrupts among multiple processors
US20070106827A1 (en) * 2005-11-08 2007-05-10 Boatright Bryan D Centralized interrupt controller
JP2009534719A (en) * 2006-01-04 2009-09-24 エヌエックスピー ビー ヴィ Interrupt distribution method and system in multiprocessor system
US20070256076A1 (en) * 2006-04-27 2007-11-01 Thompson James W System and method for separating multiple workloads processing in a single computer operating environment
US7634642B2 (en) * 2006-07-06 2009-12-15 International Business Machines Corporation Mechanism to save and restore cache and translation trace for fast context switch
JP5243711B2 (en) * 2006-11-10 2013-07-24 セイコーエプソン株式会社 Processor
US7627706B2 (en) * 2007-09-06 2009-12-01 Intel Corporation Creation of logical APIC ID with cluster ID and intra-cluster ID
US7962679B2 (en) * 2007-09-28 2011-06-14 Intel Corporation Interrupt balancing for multi-core and power
US8359561B2 (en) * 2007-12-06 2013-01-22 Onespin Solutions Gmbh Equivalence verification between transaction level models and RTL at the example to processors
US7685347B2 (en) * 2007-12-11 2010-03-23 Xilinx, Inc. Interrupt controller for invoking service routines with associated priorities
DE102008005124A1 (en) * 2008-01-18 2009-07-23 Kuka Roboter Gmbh Computer system, control device for a machine, in particular for an industrial robot, and industrial robots
CN101546276B (en) * 2008-03-26 2012-12-19 国际商业机器公司 Method for achieving interrupt scheduling under multi-core environment and multi-core processor
US20090320031A1 (en) * 2008-06-19 2009-12-24 Song Justin J Power state-aware thread scheduling mechanism
US20090327556A1 (en) * 2008-06-27 2009-12-31 Microsoft Corporation Processor Interrupt Selection
US7996595B2 (en) 2009-04-14 2011-08-09 Lstar Technologies Llc Interrupt arbitration for multiprocessors
US8321614B2 (en) * 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050010707A1 (en) * 2003-07-07 2005-01-13 Arm Limited Data processing apparatus and method for handling interrupts
US20060026322A1 (en) * 2004-07-27 2006-02-02 Texas Instruments Incorporated Interrupt management in dual core processors

Also Published As

Publication number Publication date
EP2488953A2 (en) 2012-08-22
US8234431B2 (en) 2012-07-31
JP2013507719A (en) 2013-03-04
WO2011046895A2 (en) 2011-04-21
JP5492305B2 (en) 2014-05-14
US20110087815A1 (en) 2011-04-14
EP2488953A4 (en) 2014-08-06
EP2488953B1 (en) 2016-11-30

Similar Documents

Publication Publication Date Title
WO2011046895A3 (en) Interrupt masking for multi-core processors
TW201714103A (en) Application scheduling in heterogeneous multiprocessor computing platforms for maximal predicted performance gains
WO2012109564A3 (en) Techniques for managing power consumption state of a processor
GB2520852A (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
ATE530986T1 (en) INTERRUPTION ARBITRATION FOR MULTIPROCESSORS
WO2011084330A3 (en) System and method for controlling central processing unit power with guaranteed transient deadlines
GB2519017A (en) Next instruction access intent instruction
WO2012025827A3 (en) Assignment of priorities of applications and processes according to user-specific usage patterns
GB2523494A (en) Managing a power state of a processor
IN2012DN00929A (en)
WO2013090773A3 (en) Policies for shader resource allocation in a shader core
WO2012087971A3 (en) Descriptor scheduler
GB2498046B (en) Controlling the use of computing resources in database as a service
MX348648B (en) Constrained transaction execution.
GB2496765A (en) Systems and methods for scheduling driver interface tasks based on driver workload
WO2009076531A3 (en) Shared interrupt controller for a multi-threaded processor
WO2012125200A3 (en) Dynamic core selection for heterogeneous multi-core systems
WO2013049762A3 (en) Multi-core microprocessor reliability optimization
ATE514998T1 (en) CLOCKED PORTS
GB0802801D0 (en) Increasing workload performance of one or more cores on multiple core processors
WO2011031357A8 (en) Mapping of computer threads onto heterogeneous resources
WO2012040632A3 (en) Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions
EP2664977A3 (en) Leakage variation aware power management for multicore processors
NZ598027A (en) Service dependency notification system
EP2746957A3 (en) Intelligent interrupt distributor

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2012534273

Country of ref document: JP

REEP Request for entry into the european phase

Ref document number: 2010823917

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2010823917

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10823917

Country of ref document: EP

Kind code of ref document: A2