WO2011063292A3 - Semiconductor device having strain material - Google Patents
Semiconductor device having strain material Download PDFInfo
- Publication number
- WO2011063292A3 WO2011063292A3 PCT/US2010/057514 US2010057514W WO2011063292A3 WO 2011063292 A3 WO2011063292 A3 WO 2011063292A3 US 2010057514 W US2010057514 W US 2010057514W WO 2011063292 A3 WO2011063292 A3 WO 2011063292A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- source
- strain material
- drain
- cell
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 239000000463 material Substances 0.000 title abstract 4
- 238000002955 isolation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012540112A JP5684280B2 (en) | 2009-11-19 | 2010-11-19 | Semiconductor device with strained material |
CN201080061272.2A CN102714183B (en) | 2009-11-19 | 2010-11-19 | Semiconductor device having strain material |
KR1020127015744A KR101350846B1 (en) | 2009-11-19 | 2010-11-19 | Semiconductor device having strain material |
EP10782788A EP2502267A2 (en) | 2009-11-19 | 2010-11-19 | Semiconductor device having strain material |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/621,736 US8159009B2 (en) | 2009-11-19 | 2009-11-19 | Semiconductor device having strain material |
US12/621,736 | 2009-11-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011063292A2 WO2011063292A2 (en) | 2011-05-26 |
WO2011063292A3 true WO2011063292A3 (en) | 2012-07-05 |
Family
ID=43502595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2010/057514 WO2011063292A2 (en) | 2009-11-19 | 2010-11-19 | Semiconductor device having strain material |
Country Status (6)
Country | Link |
---|---|
US (2) | US8159009B2 (en) |
EP (1) | EP2502267A2 (en) |
JP (1) | JP5684280B2 (en) |
KR (1) | KR101350846B1 (en) |
CN (1) | CN102714183B (en) |
WO (1) | WO2011063292A2 (en) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350253B1 (en) * | 2010-01-29 | 2013-01-08 | Xilinx, Inc. | Integrated circuit with stress inserts |
US8765491B2 (en) * | 2010-10-28 | 2014-07-01 | International Business Machines Corporation | Shallow trench isolation recess repair using spacer formation process |
US9564361B2 (en) | 2013-09-13 | 2017-02-07 | Qualcomm Incorporated | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
US9196613B2 (en) * | 2013-11-19 | 2015-11-24 | International Business Machines Corporation | Stress inducing contact metal in FinFET CMOS |
KR102219096B1 (en) * | 2014-08-06 | 2021-02-24 | 삼성전자주식회사 | Semiconductor device to which pattern structure for performance improvement is applied |
KR102181686B1 (en) | 2014-12-04 | 2020-11-23 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
US9362275B1 (en) * | 2015-02-13 | 2016-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with dummy gate structures |
US9818873B2 (en) * | 2015-10-09 | 2017-11-14 | Globalfoundries Inc. | Forming stressed epitaxial layers between gates separated by different pitches |
US9991167B2 (en) * | 2016-03-30 | 2018-06-05 | Globalfoundries Inc. | Method and IC structure for increasing pitch between gates |
US9946674B2 (en) | 2016-04-28 | 2018-04-17 | Infineon Technologies Ag | Scalable multi-core system-on-chip architecture on multiple dice for high end microcontroller |
KR102629347B1 (en) * | 2016-12-08 | 2024-01-26 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
US10331924B2 (en) | 2016-12-14 | 2019-06-25 | Reliant Immune Diagnostics, Inc. | System and method for audiovisual response to retail diagnostic product |
US11599908B2 (en) | 2016-12-14 | 2023-03-07 | Reliant Immune Diagnostics, Inc. | System and method for advertising in response to diagnostic test |
US10527555B2 (en) | 2016-12-14 | 2020-01-07 | Reliant Immune Disgnostics, Inc. | System and method for visual trigger to perform diagnostic test |
US11170877B2 (en) * | 2016-12-14 | 2021-11-09 | Reliant Immune Diagnostics, LLC | System and method for correlating retail testing product to medical diagnostic code |
US11594337B2 (en) | 2016-12-14 | 2023-02-28 | Reliant Immune Diagnostics, Inc. | System and method for advertising in response to diagnostic test results |
CN108574013B (en) * | 2017-03-13 | 2021-07-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of operating the same |
US10861553B2 (en) * | 2018-09-27 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device-region layout for embedded flash |
DE102019112410A1 (en) | 2018-09-27 | 2020-04-02 | Taiwan Semiconductor Manufacturing Co. Ltd. | Device area layout for embedded flash memory |
CN112151379B (en) * | 2019-06-28 | 2023-12-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080079097A1 (en) * | 2006-09-29 | 2008-04-03 | Hideki Inokuma | Semiconductor device and method of fabricating the same |
US20080296693A1 (en) * | 2007-05-31 | 2008-12-04 | Ralf Richter | Enhanced transistor performance of n-channel transistors by using an additional layer above a dual stress liner in a semiconductor device |
US20090001526A1 (en) * | 2007-06-29 | 2009-01-01 | Frank Feustel | Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines |
US20090081563A1 (en) * | 2007-09-25 | 2009-03-26 | Helen Wang | Integrated Circuits and Methods of Design and Manufacture Thereof |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003086708A (en) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
JP3855793B2 (en) * | 2002-02-18 | 2006-12-13 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
JP4030383B2 (en) * | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
JP3897730B2 (en) * | 2003-04-23 | 2007-03-28 | 松下電器産業株式会社 | Semiconductor memory device and semiconductor integrated circuit |
US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US7484198B2 (en) * | 2006-02-27 | 2009-01-27 | Synopsys, Inc. | Managing integrated circuit stress using dummy diffusion regions |
JP5310543B2 (en) * | 2007-03-27 | 2013-10-09 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US7923365B2 (en) * | 2007-10-17 | 2011-04-12 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
DE102007052051B4 (en) * | 2007-10-31 | 2012-09-20 | Advanced Micro Devices, Inc. | Fabrication of stress-inducing layers over a device region with dense transistor elements |
JP5268385B2 (en) | 2008-02-13 | 2013-08-21 | パナソニック株式会社 | Semiconductor device |
US7902878B2 (en) * | 2008-04-29 | 2011-03-08 | Qualcomm Incorporated | Clock gating system and method |
-
2009
- 2009-11-19 US US12/621,736 patent/US8159009B2/en active Active
-
2010
- 2010-11-19 CN CN201080061272.2A patent/CN102714183B/en active Active
- 2010-11-19 WO PCT/US2010/057514 patent/WO2011063292A2/en active Application Filing
- 2010-11-19 KR KR1020127015744A patent/KR101350846B1/en active IP Right Grant
- 2010-11-19 EP EP10782788A patent/EP2502267A2/en not_active Withdrawn
- 2010-11-19 JP JP2012540112A patent/JP5684280B2/en not_active Expired - Fee Related
-
2012
- 2012-04-17 US US13/448,786 patent/US20130099851A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080079097A1 (en) * | 2006-09-29 | 2008-04-03 | Hideki Inokuma | Semiconductor device and method of fabricating the same |
US20080296693A1 (en) * | 2007-05-31 | 2008-12-04 | Ralf Richter | Enhanced transistor performance of n-channel transistors by using an additional layer above a dual stress liner in a semiconductor device |
US20090001526A1 (en) * | 2007-06-29 | 2009-01-01 | Frank Feustel | Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines |
US20090081563A1 (en) * | 2007-09-25 | 2009-03-26 | Helen Wang | Integrated Circuits and Methods of Design and Manufacture Thereof |
Non-Patent Citations (1)
Title |
---|
PINA C A ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Implementation of a MCM brokerage service", PROCEEDINGS OF THE MULTI CHIP MODULE CONFERENCE (MCMC). SANTA CRUZ, MAR. 15 - 18, 1993; [PROCEEDINGS OF THE MULTI CHIP MODULE CONFERENCE (MCMC)], LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. CONF. 2, 15 March 1993 (1993-03-15), pages 46 - 51, XP010095460, ISBN: 978-0-8186-3540-3, DOI: 10.1109/MCMC.1993.302153 * |
Also Published As
Publication number | Publication date |
---|---|
US20130099851A1 (en) | 2013-04-25 |
KR20120095433A (en) | 2012-08-28 |
WO2011063292A2 (en) | 2011-05-26 |
CN102714183A (en) | 2012-10-03 |
JP5684280B2 (en) | 2015-03-11 |
US20110115000A1 (en) | 2011-05-19 |
EP2502267A2 (en) | 2012-09-26 |
KR101350846B1 (en) | 2014-01-13 |
US8159009B2 (en) | 2012-04-17 |
CN102714183B (en) | 2015-05-13 |
JP2013511850A (en) | 2013-04-04 |
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