WO2011087572A3 - Offset field grid for efficient wafer layout - Google Patents

Offset field grid for efficient wafer layout Download PDF

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Publication number
WO2011087572A3
WO2011087572A3 PCT/US2010/057381 US2010057381W WO2011087572A3 WO 2011087572 A3 WO2011087572 A3 WO 2011087572A3 US 2010057381 W US2010057381 W US 2010057381W WO 2011087572 A3 WO2011087572 A3 WO 2011087572A3
Authority
WO
WIPO (PCT)
Prior art keywords
die
wafer
techniques
row
column
Prior art date
Application number
PCT/US2010/057381
Other languages
French (fr)
Other versions
WO2011087572A2 (en
Inventor
Alejandro Varela
Troy L. Harling
Daniel E. Vanlare
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to EP20100843415 priority Critical patent/EP2517227A4/en
Priority to CN201080059026.3A priority patent/CN102656668B/en
Priority to KR1020127016135A priority patent/KR101370114B1/en
Publication of WO2011087572A2 publication Critical patent/WO2011087572A2/en
Publication of WO2011087572A3 publication Critical patent/WO2011087572A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.
PCT/US2010/057381 2009-12-23 2010-11-19 Offset field grid for efficient wafer layout WO2011087572A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP20100843415 EP2517227A4 (en) 2009-12-23 2010-11-19 Offset field grid for efficient wafer layout
CN201080059026.3A CN102656668B (en) 2009-12-23 2010-11-19 Offset field grid for efficient wafer layout
KR1020127016135A KR101370114B1 (en) 2009-12-23 2010-11-19 Offset field grid for efficient wafer layout

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/646,459 2009-12-23
US12/646,459 US8148239B2 (en) 2009-12-23 2009-12-23 Offset field grid for efficient wafer layout

Publications (2)

Publication Number Publication Date
WO2011087572A2 WO2011087572A2 (en) 2011-07-21
WO2011087572A3 true WO2011087572A3 (en) 2011-09-15

Family

ID=44149891

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/057381 WO2011087572A2 (en) 2009-12-23 2010-11-19 Offset field grid for efficient wafer layout

Country Status (6)

Country Link
US (1) US8148239B2 (en)
EP (1) EP2517227A4 (en)
KR (1) KR101370114B1 (en)
CN (1) CN102656668B (en)
TW (1) TWI420584B (en)
WO (1) WO2011087572A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148239B2 (en) 2009-12-23 2012-04-03 Intel Corporation Offset field grid for efficient wafer layout
CN105849916B (en) * 2013-10-29 2019-06-25 亮锐控股有限公司 Separate the chip of luminescent device
US9165832B1 (en) 2014-06-30 2015-10-20 Applied Materials, Inc. Method of die singulation using laser ablation and induction of internal defects with a laser
US9093518B1 (en) * 2014-06-30 2015-07-28 Applied Materials, Inc. Singulation of wafers having wafer-level underfill
SG11201810017VA (en) * 2016-06-02 2018-12-28 Universal Instruments Corp Semiconductor die offset compensation variation
US20180158788A1 (en) * 2016-12-01 2018-06-07 Avery Dennison Retail Information Services, Llc Mixed structure method of layout of different size elements to optimize the area usage on a wafer
EP3985715A4 (en) * 2020-06-01 2022-11-09 Changxin Memory Technologies, Inc. Design method for wafer layout and lithography machine exposure system
CN111830793B (en) * 2020-06-22 2023-07-18 中国科学院微电子研究所 Method and system for setting wafer exposure projection diagram
EP3992715B1 (en) 2020-09-09 2023-05-31 Changxin Memory Technologies, Inc. Wafer chip layout calculation method, medium and apparatus
CN114239467A (en) * 2020-09-09 2022-03-25 长鑫存储技术有限公司 Wafer chip layout calculation method, device, medium and equipment

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS59220947A (en) * 1983-05-30 1984-12-12 Sharp Corp Manufacture of semiconductor device
US6528864B1 (en) * 1999-11-19 2003-03-04 Disco Corporation Semiconductor wafer having regular or irregular chip pattern and dicing method for the same
US7488668B2 (en) * 2004-07-23 2009-02-10 Panasonic Corporation Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions

Family Cites Families (14)

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US3169837A (en) * 1963-07-31 1965-02-16 Int Rectifier Corp Method of dicing semiconductor wafers
US5217916A (en) * 1989-10-03 1993-06-08 Trw Inc. Method of making an adaptive configurable gate array
US5128737A (en) * 1990-03-02 1992-07-07 Silicon Dynamics, Inc. Semiconductor integrated circuit fabrication yield improvements
JPH0465859A (en) * 1990-07-06 1992-03-02 Fujitsu Ltd Wafer-scale integrated circuit and signal propagation path forming method in the circuit
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
JP2874682B2 (en) * 1997-03-12 1999-03-24 日本電気株式会社 Semiconductor device
US6303899B1 (en) * 1998-12-11 2001-10-16 Lsi Logic Corporation Method and apparatus for scribing a code in an inactive outer clear out area of a semiconductor wafer
US6420245B1 (en) * 1999-06-08 2002-07-16 Kulicke & Soffa Investments, Inc. Method for singulating semiconductor wafers
US6521513B1 (en) * 2000-07-05 2003-02-18 Eastman Kodak Company Silicon wafer configuration and method for forming same
AUPR174800A0 (en) * 2000-11-29 2000-12-21 Australian National University, The Semiconductor processing
JP4330821B2 (en) * 2001-07-04 2009-09-16 株式会社東芝 Manufacturing method of semiconductor device
US6784070B2 (en) * 2002-12-03 2004-08-31 Infineon Technologies Ag Intra-cell mask alignment for improved overlay
JP4856931B2 (en) 2004-11-19 2012-01-18 キヤノン株式会社 Laser cleaving method and laser cleaving apparatus
US8148239B2 (en) 2009-12-23 2012-04-03 Intel Corporation Offset field grid for efficient wafer layout

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220947A (en) * 1983-05-30 1984-12-12 Sharp Corp Manufacture of semiconductor device
US6528864B1 (en) * 1999-11-19 2003-03-04 Disco Corporation Semiconductor wafer having regular or irregular chip pattern and dicing method for the same
US7488668B2 (en) * 2004-07-23 2009-02-10 Panasonic Corporation Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CHEN-FU CHIEN ET AL.: "A Cutting Algorithm for Optimizing the Wafer Exposure Pattern", IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, vol. 14, no. 2, May 2001 (2001-05-01), XP008155100 *
See also references of EP2517227A4 *

Also Published As

Publication number Publication date
CN102656668A (en) 2012-09-05
KR20120099261A (en) 2012-09-07
WO2011087572A2 (en) 2011-07-21
US8148239B2 (en) 2012-04-03
TW201137961A (en) 2011-11-01
US20110147897A1 (en) 2011-06-23
EP2517227A2 (en) 2012-10-31
TWI420584B (en) 2013-12-21
KR101370114B1 (en) 2014-03-04
EP2517227A4 (en) 2015-04-22
CN102656668B (en) 2015-02-25

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