WO2011140728A1

WO2011140728A1 - Differential analog front end apparatus for low frequency signal detection and transmission system

Info

Publication number: WO2011140728A1
Application number: PCT/CN2010/073665
Authority: WO
Inventors: 赵辉; 潘文杰; 蒋宇
Original assignee: 国民技术股份有限公司
Priority date: 2010-05-10
Filing date: 2010-06-08
Publication date: 2011-11-17
Also published as: CN103023445A; CN103023445B

Abstract

A differential analog front end apparatus for low frequency signal detection and transmission system is provided by the present invention, which is applied to the short-distance communication system. The front end apparatus includes at least one magnetic induction module, at least one low-pass filter module, at least one amplifier, at least one digital/analog converter and at least one comparator, wherein said magnetic induction module, low-pass filter module and amplifier are connected in sequence. The output terminal of said amplifier connects with the positive going input terminal of said comparator. The output terminal of said digital/analog converter connects with the reserve input terminal of said comparator. Said amplifier is a differential amplifier. The present invention can reduce the interference to the received low frequency signal in the low frequency signal diction and transmission system caused by circuit noise and environment noise, thereby improving the precision of distance detection and control for low frequency alternating magnetic field.

Description

Differential analog front end device for low frequency signal detection and transmission system

The present invention relates to the field of communications, and more particularly to a differential analog front end apparatus for a low frequency signal detection and transmission system, and a method for detecting a low frequency signal using the apparatus. Background technique

Nowadays, there has been a radio frequency function (called a radio frequency SIM card) on the SIM (Subscr iber Ident I ty Module) card in the mobile phone or a short-range communication module on the mobile phone motherboard to realize the short-range communication of the mobile phone. The method, the emergence of this method makes the mobile phone a super smart terminal that can be recharged, consumed, traded and authenticated, which greatly meets the urgent needs of the market.

Among them, the RF SIM-based mobile phone proximity solution has received extensive attention due to its advantages such as the single-sheet and no need to change the mobile phone. In this solution, the RF SIM adopts UHF (Ultra-Ra High Frequency) technology to make the RF. RF signal is still embedded when the SIM card is embedded inside the phone

It can make the mobile phone have close-range communication function. However, different mobile phones have large differences in the transmission effect of radio frequency signals due to different internal structures. The radio frequency SIM card radio communication distance of a mobile phone with strong transmission may reach a distance of several meters, and the radio frequency S IM card communication distance of a mobile phone with weak transmission can also A few tens of centimeters. In mobile payment applications, such as bus and subway card, there are usually strict requirements on the transaction distance to ensure the security of the transaction, such as the transaction distance requirement is limited to 10cm or less, in order to prevent users from accidentally brushing and causing losses; On the other hand, it is also required to ensure the reliability of communication below the prescribed distance to improve the efficiency of the transaction. Therefore, mobile phone SIM-based mobile phones must be able to effectively control the distance range of their transactions while increasing the short-range communication function. Therefore, a system and method for low-frequency alternating magnetic field short-range communication combined with RF high-frequency communication is proposed, which solves the above problems. The system uses low-frequency alternating magnetic field to realize distance detection and control, and realizes one-way communication between the card reader and the card. The RF channel is combined with low-frequency communication to achieve reliable binding of the terminal, and the RF channel is used to realize the card reader and the card. High-speed data communication. However, in this scheme, the low-frequency signal received by the low-frequency signal detection and transmission system (on one side of the card) is mixed with circuit noise and environmental noise, which affects the accuracy of distance detection and control. Therefore, how to effectively reduce the circuit The interference of noise and environmental noise on low-frequency signals has become one of the urgent problems to be solved. Summary of the invention

The technical problem to be solved by the present invention is to provide a differential analog front end device for a low frequency signal detection and transmission system, which reduces the interference of circuit noise and environmental noise on low frequency signal detection and low frequency signals received in the transmission system, and improves The accuracy of low frequency alternating magnetic field distance detection and control.

In order to solve the above technical problem, the present invention provides a differential analog front end device for a low frequency signal detection and transmission system, which is applied to a short-range communication system, including at least one magnetic induction module, at least one low-pass filter module, at least one amplifier, At least one digital/analog converter and at least one comparator, the magnetic induction module, the low pass filtering module, and the amplifier are sequentially connected, and an output end of the amplifier is connected to a forward input end of the comparator, the number / An output of the analog converter is coupled to an inverting input of the comparator, the amplifier being a differential amplifier.

Further, the above device may further have the following features, including a magnetic induction module, a low pass filter module, an amplifier, two digital/analog converters, and two comparators, the magnetic induction module, the low pass filter module, and the amplifier Connected once, the output of the amplifier is respectively connected to the forward input terminals of the two comparators, and the two digital/analog converters and the two comparators form two paths, each of which is digital/analog The output of the converter is connected to the inverting input of the comparator, and each pair of the upper and lower channels form a pair, a pair.

Further, the above device may also have the following features, including a magnetic induction module, a low a pass filter module, an amplifier, six digital/analog converters, and six comparators, the outputs of which are respectively connected to the forward inputs of the six comparators, the six digital/analog converters The six comparators are combined with the six comparators, and the output of each of the digital/analog converters is connected to the inverting input of the comparator, and each pair of upper and lower channels is paired, and three pairs are provided.

Further, the above device may further have the following features: the magnetic induction module is a differential magnetic induction line, a differential Hall device or a differential giant magnetoresistive device.

Further, the device may further have the following feature: the magnetic induction module is a differential magnetic induction coil, and the two output ends of the differential magnetic induction coil are directly connected to the two input ends of the low-pass filter module.

Further, the device may further have the following feature, the magnetic induction module is a differential Hall device, and two output ends of the differential Hall device are connected to two input ends of the low-pass filter module through a DC blocking capacitor; or One output end of the differential Hall device is connected to one input end of the low pass filter module through a DC blocking capacitor, and the other output end of the differential Hall device is directly connected to another input end of the low pass filter module; or The two outputs of the differential Hall device are directly connected to the two inputs of the low pass filter module.

Further, the above device may further have the following feature, the magnetic induction module is a differential giant magnetoresistive device, and two output ends of the differential giant magnetoresistive device pass through a DC blocking capacitor and two input ends of the low pass filter module Connected; or an output of the differential giant magnetoresistive device is connected to one input of the low pass filter module through a DC blocking capacitor, and the other output of the differential giant magnetoresistive device is directly connected to the low pass The other input of the filter module is connected; or the two outputs of the differential giant magnetoresistive device are directly connected to the two inputs of the low pass filter module.

Further, the above device may further have the following features: the amplifier is a single-stage differential amplifier or a multi-stage cascaded differential amplifier connected to a resistor negative feedback network.

Further, the above device may further have the following features, the amplifier is a four-stage cascaded differential amplifier, and the composition of the four-stage cascaded differential amplifier is: The first stage comprises a first differential amplifier, a resistor R _al, resistors R _bl, resistance R _all, the resistance R _bll, capacitance and the capacitance C _u; is a termination resistor R _al AINP phase signal input port, the other end of the resistor Rbi, the other end of said inverted output terminal of the first resistor R _BL differential amplifier, the resistor R and the resistor R _BL _Al contacts connected with said first differential amplifier input terminal, a capacitor connected in parallel with the resistor R _BL, the resistor R _all of inverting a signal input port AINN end, the other end of the resistor R _bll, the other end of the resistor R _bll with a first differential amplifier connected to said first contact output terminal, and a resistor R _all of the resistance R _bll An inverting input of a differential amplifier, the capacitor C _u being connected in parallel with the resistor R _b11 ;

The second stage includes a second differential amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _a21 , a resistor R _b21 , a capacitor C ₂ and a capacitor C ₂₁ ; one end of the capacitor C ₂ is connected to the reverse output of the first differential amplifier The other end is connected to the resistor R _a2 , the other end of the resistor R _a2 is connected to the non-inverting input end of the second differential amplifier, and the resistor R _{b2 is} connected between the non-inverting input terminal and the opposite output end of the second differential amplifier One end of the capacitor C ₂₁ is connected to the same output end of the first differential amplifier, the other end is connected to the resistor R _a21 , and the other end of the resistor R _a21 is connected to the inverting input end of the second differential amplifier, and the resistor R _{b21 is} connected Between the inverting input terminal and the non-inverting output terminal of the second differential amplifier;

The third stage includes a third differential amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _a31 , a resistor R _b31 , a capacitor C _{3 ,} and a capacitor C ₃₁ ; a resistor R _{a3 is} connected to the inverting output of the second differential amplifier and Between the non-inverting input terminals of the third differential amplifier, a resistor R _b3 and a capacitor C ₃ are connected in parallel between the non-inverting input terminal and the non-inverting output terminal of the third differential amplifier, and the resistor R _{a31 is} connected to the first Between the non-inverting output of the two differential amplifiers and the inverting input of the third differential amplifier, a resistor R _b31 and a capacitor C ₃₁ are connected in parallel between the inverting input terminal and the non-inverting output terminal of the third differential amplifier ;

The fourth stage includes a fourth amplifier, a resistor R _a4 , a resistor R _b4 , a resistor R _a41 , a resistor R _b41 , a capacitor C _{4 ,} and a capacitor C ₄₁ ; one end of the capacitor C ₄ is connected to an inverting output of the third differential amplifier, The other end is connected to the resistor R _a4 , the other end of the resistor R _a4 is connected to the inverting input end of the fourth amplifier, and the resistor R _{b4 is} connected between the inverting input terminal and the output end of the fourth amplifier, the capacitor C ₄₁ One end is connected to the same output end of the third differential amplifier, the other end is connected to the resistor R _a41 , and the other end of the resistor R _a41 is connected to the fourth amplification The non-inverting input of the device, the resistor R _{M1 is} connected between the non-inverting input terminal of the fourth amplifier and the ground. Further, the above device may further have the following features, the amplifier is a four-stage cascaded differential amplifier, and the composition of the four-stage cascaded differential amplifier is:

The first stage comprises a first differential amplifier, a resistor R _al, resistors R _bl, R _all resistors and the resistor R _bll; terminating resistor R _al is a positive-phase signal input port AINP, the other end of the resistor R _bl, another resistor R _bl one end of said inverted output terminal of the first differential amplifier, and a resistor R _al ₁ ¾1 the contact resistance of the first differential amplifier connected to one end of the same signal input port AINN inverting input terminal, a resistor R _all of the other One end is connected to the resistor R _b11 , the other end of the resistor R _b11 is connected to the same output end of the first differential amplifier, and the contact of the resistor R _all and the resistor R _b11 is connected to the opposite input end of the first differential amplifier;

The second stage includes a second differential amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _a21 , a resistor R _b21 , a resistor ε _ε1 , a resistor R _ell , a capacitor d , a capacitor C ₂ , a capacitor C _{u ,} and a capacitor C ₂₁ ; The capacitor C ₂ and the resistor R _a2 are sequentially connected in series between the inverting output terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier, and the capacitor is connected to the junction of the resistor and the capacitor C ₂ . Between the ground, a resistor R _{b2 is} connected between the non-inverting input terminal and the inverting output terminal of the second differential amplifier, and the resistor Ren, the capacitor C ₂₁ and the resistor ₂₁ are sequentially connected in series in the same direction of the first differential amplifier Between the output terminal and the inverting input terminal of the second differential amplifier, a capacitor C _{u is} connected between the junction of the resistor and the capacitor C ₂₁ and the ground, and the resistor R _{b21 is} connected to the inverting input terminal of the second differential amplifier. Between the same direction output;

The third stage includes a third differential amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _{a31 ,} and a resistor R _b31 ; one end of the resistor R _a3 is connected to the opposite output end of the second differential amplifier, and the other end is connected to the resistor R _b3 , The other end of the resistor R _b3 is connected to the inverting output end of the third differential amplifier, and the contact of the resistor R _a3 and the resistor R _b3 is connected to the non-inverting input end of the third differential amplifier, and one end of the resistor R _a31 is connected to the first The same output of the two differential amplifiers, the other end is connected to the resistor R _b31 , the other end of the resistor R _b31 is connected to the same output end of the third differential amplifier, and the junction of the resistor R ₃₁ and the resistor R _b31 is connected to the third differential The inverting input of the amplifier; The fourth stage includes a fourth amplifier, a resistor R _a4 , a resistor R _b4 , a resistor R _a41 , a resistor R _b41 , a resistor Rc2 , a resistor Rc ₂₁ , a capacitor C ₃ , a capacitor C ₄ , a capacitor C _{31 ,} and a capacitor C ₄₁ ; _{2. The} capacitor C ₄ and the resistor R _a4 are sequentially connected in series between the inverting output terminal of the third differential amplifier and the inverting input terminal of the fourth amplifier, and the capacitor C _{3 is} connected to the resistor R. ₂ and the junction of the capacitor C ₄ and the ground, the resistor R _{b4 is} connected between the inverting input terminal and the output terminal of the fourth amplifier, the resistor R. ₂₁ , a capacitor C ₄₁ and a resistor R _a41 are sequentially connected in series between the non-inverting output terminal of the third differential amplifier and the non-inverting input terminal of the fourth amplifier, and the capacitor C _{31 is} connected to the resistor R. _{21 is} connected between the junction of capacitor C ₄₁ and ground, and resistor R _{b41 is} connected between the non-inverting input of said fourth amplifier and ground.

Further, the above device may further have the following features, the amplifier is a three-stage cascaded differential amplifier, and the three-stage cascaded differential amplifier has the following components:

The first stage comprises a first differential amplifier, a resistor R _al, R _bl resistance, resistance R _all, the resistance R _bll, capacitance and the capacitance C _u; is a termination resistor R _al AINP phase signal input port, the other end of the resistor R _bl , the other end of said inverted output terminal of the first resistor R _bl differential amplifier, and a resistor R _al resistors R _bl contacts connected with said first differential amplifier input terminal, a capacitor connected in parallel with the resistor R _bl, resistance One end of R _all is connected to the reverse signal input port AINN, and the other end is connected to the resistor R _bll . The other end of the resistor 1 3 ₄₁₁ is connected to the same output end of the first differential amplifier, and the contact of the resistor R _all and the resistor R _b11 is connected. a non-inverting input of the first differential amplifier, the capacitor C _u is connected in parallel with the resistor R _b11 ;

The second stage includes a second differential amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _a21 , a resistor R _b21 , a capacitor C ₂ , a capacitor C ₃ , a capacitor C _{21 ,} and a capacitor C ₃₁ ; the capacitor C ₂ and the resistor R _a2 are sequentially connected in series with said first differential amplifier and the inverted output terminal of the differential amplifier between the second input terminal, the capacitor C ₃ and resistor R _b2 anti-parallel to the input terminal and the second differential amplifier with Between the output terminals, a capacitor C ₂₁ and a resistor R _a21 are sequentially connected in series between the inverting output terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier, a capacitor C ₃₁ and a resistor R _{b21 .} Parallel between the non-inverting input and the inverting output of the second differential amplifier;

The third stage includes a third amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _a31 , a resistor R _b31 , a capacitor C ₄ and capacitor C ₄₁ ; capacitor C ₄ and resistor ₃ are sequentially connected in series between the inverting output of the second differential amplifier and the non-inverting input of the third amplifier, capacitor C ₄₁ and resistor R _a31 a second series connection between the non-inverting output of the second differential amplifier and the inverting input of the third amplifier, and a resistor R _b3 connected between the non-inverting input and the output of the third amplifier, the resistor R _{b31 is} connected between the inverting input of the third amplifier and ground.

Further, the above device may further have the following features: the digital/analog converter is a current mode R2R structure, and the output range of the digital/analog converter is at most one-half of the power supply ground voltage.

Further, the above device may further have the following features, the digital/analog converter is a current mode R2R structure, and the output range of the digital/analog converter is not limited to one-half of the power supply ground voltage, and the common mode level adjustable.

Further, the above device may also have the following features, the digital/analog converter is a voltage mode R2R structure, and the output range of the digital/analog converter is not limited to one-half of the power supply ground voltage.

Further, the above device may also have the following features, the digital/analog converter is an R2R network structure, and the output range of the digital/analog converter is as large as the power supply ground voltage.

Further, the above device may further have the following features, the comparator for comparing the high level includes three NM0S tubes MnO, Mnl, Mn2 and two PM0 tubes Mpl, Mp2, and an inverter, PM0S tubes Mpl and PM0S The gate of the tube Mp2 is connected, the source is connected to the power supply Vcc, the drain of the PM0S tube Mpl is connected to the drain of the LV1, and the source of the MN1 and Mn2 are connected to the drain of the MNO. The drain of the MOS transistor Mn2 is connected to the drain of the PM0S transistor Mp2, the source of the MOS transistor MnO is grounded to GND, the gate is connected to the bias voltage Vbn, and the input terminal of the inverter is connected to the drain of the PM0S transistor Mp2. The gate of the OS tube Mn2 is the forward input terminal Vin+ of the comparator, the gate of the NMOS transistor Mn1 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator.

Further, the above device may further have the following features, and the comparator for comparing the low level includes Three PMOS transistors M _P 0, Mp3, Mp4 and two NMOS transistors Mn3, Mn4 and an inverter, the source of the PMOS transistor MpO is connected to the power supply Vcc, the gate is connected to the bias voltage Vbp, and the drain is connected to the PMOS transistor M. PMOS transistor _P 3 and 4 M _P source electrode, the drain of PMOS transistor M _P Li drain and a gate connected to Mn3 tube 3 OS, OS tube Mn3 Li and Li source OS tube Mn4 the GND is grounded, Korea OS tube The drain of Mn4 is connected to the drain of PMOS transistor M _P 4 , the input end of the inverter is connected to the drain of NMOS transistor Mn4 , and the gate of PMOS transistor M _P 4 is the forward input terminal of the comparator Vin+, PMOS transistor M _P The gate of 3 is the inverting input Vin_ of the comparator, and the output of the inverter is the output Vo of the comparator.

In order to solve the above technical problem, the present invention also proposes a low frequency signal detecting method based on the above differential analog front end device for a low frequency signal detecting and transmitting system, comprising:

Step a, through experiment, measuring the voltage amplitude of the induced voltage of the magnetic induction module and the card reader transmitting the low frequency magnetic field at different distance points, and determining the corresponding relationship between the voltage amplitude and the distance, and establishing the voltage amplitude and Correspondence table of distances;

Step b, according to the need of decoding the low frequency signal to transmit data and control the swipe distance, combined with the signal to noise ratio requirement, the hysteresis decision voltage threshold is formed by the bi-level threshold outputted by one or more pairs of digital-to-analog converters to determine the analog signal, The code stream information transmitted by the low-frequency magnetic field, or the single-level threshold outputted by one or more digital-to-analog converters forms a decision voltage threshold to determine the analog signal, and obtains the code stream information transmitted by the low-frequency magnetic field; The bi-level threshold of the digital-to-analog converter output forms a non-hysteresis decision voltage threshold to determine the analog signal, obtains the distance characteristic information transmitted by the low-frequency magnetic field, or forms a single-level threshold through one or more digital-to-analog converter outputs. The non-hysteresis decision voltage threshold determines the analog signal to obtain the distance characteristic information transmitted by the low frequency magnetic field; step c, samples the signal after the non-hysteresis decision condition, obtains a 0, 1 code stream sequence, and sets a signal proportional threshold. The code stream sequence is counted within the set time window length, when the 1 signal occupies the code stream When the column ratio reaches the preset proportional threshold, it is considered to enter the preset distance range, otherwise it is considered that the distance range is not entered; the signal sequence after the decision of the hysteresis decision condition is decoded, the code stream information of the low frequency magnetic field is extracted, and the low frequency magnetic field signal signal is completed. To communication. Further, the above method may further have the following features. In the step b, according to the correspondence table of the voltage amplitude and the distance in the step a, combined with the decoding distance, the distance control requirement, and the proportional threshold of the set 1 signal, the digital mode is set. The level at which the converter outputs to the comparator.

Further, the above method may further have the following feature: the level of the pair of digital-to-analog converters outputted to the comparator is a non-hysteresis decision condition, and the setting method is: setting the distance of the desired control to D1, finding the voltage amplitude and The correspondence table of the distance obtains the signal variation range corresponding to the distance D1 from +A1 to -A1, and the proportional threshold of the set 1 signal is R1. According to A1 and R1, the levels L1 and L2 output to the comparator are set to satisfy one cycle. The percentage of time that the output front-end device output signal amplitude is greater than L1 or less than L2 is equal to R1, that is, if it is greater than R1, it enters the range of the required control distance D1, otherwise it does not enter the range of the required control distance D1.

Further, the above method may further have the following feature: the level of the pair of digital-to-analog converters outputted to the comparator is a hysteresis decision condition, and the setting method is: setting the distance to be decoded to be D2, finding the voltage amplitude and The correspondence table of the distance obtains the change range of the signal corresponding to the distance D2 from +A2 to -A2, and the amplitude of most noise is measured as A3, and the levels L3 and L4 output to the comparator are set such that L3 is greater than +A3 and smaller than +A2 ; L4 is less than -A3 and greater than -A2, that is, decoding is allowed when the distance is less than D2, otherwise decoding is not allowed.

Further, the above method may further have the following feature. In the step b, the two comparator output signals input to the non-hysteresis decision condition comparison level are logically ORed to obtain a digital signal for extracting the distance information.

Further, the above method may further have the following feature. In the step b, the two comparator outputs whose input is the hysteresis decision condition comparison level are subjected to hysteresis processing to obtain a digital signal for extracting the magnetic field code stream information.

Further, the above method may further have the following feature. In the step c, the digital glitch filter is set to perform burr filtering on the input digital signal, and the low frequency magnetic field data stream is decoded from the signal for filtering the glitch. Further, the above method may further have the following feature. In the step b, the magnetic field distance information and the code stream information are extracted using a single comparison level output by a single digital-to-analog converter.

Further, the above method may further have the following feature: using a single comparator output comparison level to extract the magnetic field code stream information, and the level of the digital-to-analog converter output to the comparator is set to the amplifier input reference level.

Further, the above method may also have the following features: decoding using a single comparator or a digital signal output by a pair of comparators.

Further, the above method may further have the following feature: using a single comparator or a digital signal output by a pair of comparators to perform a single distance determination; using a plurality of single comparator output digital signals to determine a plurality of distances, or using multiple Pairwise comparators determine multiple distances and multiple distance intervals; use multiple digital comparator output digital signals to determine multiple distances, or use multiple pairs of comparators to perform multiple distances, multiple distances Interval judgment.

Further, the above method may further have the following feature: the plurality of single comparators and the digital signals output by the paired comparators are mixed to determine the plurality of distances and the plurality of distance intervals.

The invention can reduce the interference of the circuit noise and the environmental noise on the low frequency signal received and the low frequency signal received in the transmission system, thereby improving the accuracy of the low frequency alternating magnetic field distance detection and control. DRAWINGS

1 is a structural diagram of a differential analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

2 is another structural diagram of a differential analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

3 is still another structural diagram of a differential analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention;

4 is a structural diagram of a fully differential programmable gain amplifier according to an embodiment of the present invention; 5 is a structural diagram of another fully differential programmable gain amplifier according to an embodiment of the present invention; FIG. 6 is a structural diagram of another fully differential programmable gain amplifier according to an embodiment of the present invention; a structural diagram of a digital/analog converter;

Figure 7. 2 is a structural diagram of another digital/analog converter in the embodiment of the present invention;

Figure 7.3 is a structural diagram of still another digital/analog converter in the embodiment of the present invention;

Figure 7.4 is a structural diagram of another digital/analog converter according to an embodiment of the present invention;

FIG. 8 is a structural diagram of a comparator according to an embodiment of the present invention; FIG.

FIG. 9 is a structural diagram of another comparator according to an embodiment of the present invention; FIG.

FIG. 10.1 is a structural diagram of a first magnetic induction module according to an embodiment of the present invention;

Figure 10 is a structural diagram of a second magnetic induction module according to an embodiment of the present invention;

Figure 10.3 is a structural diagram of a third magnetic induction module in the embodiment of the present invention;

Figure 10.4 is a structural diagram of a fourth magnetic induction module according to an embodiment of the present invention;

Figure 10.5 is a structural diagram of a fifth magnetic induction module according to an embodiment of the present invention;

Figure 10.6 is a structural diagram of a sixth magnetic induction module according to an embodiment of the present invention;

Figure 10 is a structural diagram of a seventh magnetic induction module according to an embodiment of the present invention;

11 is a flowchart of a method for detecting a low frequency signal according to an embodiment of the present invention;

FIG. 12 is a schematic diagram showing the correspondence between the distance and the amplitude value of the low frequency sensing signal by the magnetic induction module being placed into different mobile communication terminals according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of decoding processing using a pair of comparators using a magnetic field data low frequency signal detecting method according to an embodiment of the present invention; FIG.

14 is a schematic diagram of a distance control process using a pair of comparators using a low frequency signal detection method according to an embodiment of the present invention;

15 is a schematic diagram of decoding processing using a single comparator using a magnetic field data low frequency signal detecting method according to an embodiment of the present invention;

16 is a schematic diagram of using a single comparator to detect a distance using a low frequency signal detection method according to an embodiment of the present invention; Schematic diagram of the control process. detailed description

The main idea of the present invention is to add an analog front end device to the low frequency signal detection and transmission system to reduce the interference of circuit noise and environmental noise on low frequency signals, thereby improving the accuracy of low frequency alternating magnetic field distance detection and control.

The principles and features of the present invention are described in the following with reference to the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a differential analog front end device for a low frequency signal detection and transmission system in accordance with an embodiment of the present invention. As shown in FIG. 1, in this embodiment, a differential analog front end device of a low frequency signal detection and transmission system includes a magnetic induction module 100, a low pass filter module 104, an amplifier 101, a digital/analog converter 102, and a comparator 103, wherein The magnetic induction module 100, the low-pass filter module 104, and the amplifier 101 are sequentially connected. The output of the amplifier 101 is connected to the forward input of the comparator 103, and the output of the digital/analog converter 102 is inverted with the comparator 103. The terminals are connected, and the amplifier 101 is a differential amplifier. The amplifier 101 prevents the input weak signal from being large, and the digital/analog converter 102 converts the digital signal output by the digital controller into an analog signal, and then compares the two signals by the comparator 103 to obtain a desired digital signal, which is transmitted to Processing in the digital controller. The digital controller mentioned here belongs to the low-frequency detection and transmission system, but it is not the analog front end. Its function is to control the comparator/digital/analog converter on/off mode according to the comparator output.

2 is another structural diagram of a differential analog front end device for a low frequency signal detection and transmission system according to an embodiment of the present invention. As shown in FIG. 2, in this embodiment, the differential analog front end device of the low frequency signal detection and transmission system includes a magnetic induction module 100, a low pass filter module 104, an amplifier 101, a digital/analog converter 102, and a digital / analog converter 105 and comparator 103, comparator 106, magnetic induction module 100, low-pass filter module 104, amplifier 101 are sequentially connected, amplified The output of the comparator 101 is connected to the forward input of the comparator 103 and the comparator 106, respectively. The digital/analog converter 102, the digital/analog converter 105 and the comparator 103 and the comparator 106 form two paths, each of which is digital. The output of the /analog converter is connected to the inverting input of the comparator, and each pair of upper and lower channels form a pair, a pair.

Fig. 3 is still another structural diagram of a differential analog front end device for a low frequency signal detecting and transmitting system in accordance with an embodiment of the present invention. As shown in FIG. 3, in this embodiment, the differential analog front end device of the low frequency signal detection and transmission system includes a magnetic induction module 100, a low pass filtering module 104, an amplifier 201, and six digital/analog converters 202, 203. , 204 and six comparators 205, 206, 207, the output of the amplifier 201 is connected to the forward input of the six comparators 205, 206, 207, respectively, six digital / analog converters 202, 203, 204 and six Comparing 205, 206, and 207 devices to form a six-way circuit, the output end of each of the digital/analog converters is connected to the opposite input end of the comparator, and each pair of upper and lower channels is formed into a pair, and three pairs are provided.

4 is a structural diagram of a fully differential programmable gain amplifier in accordance with an embodiment of the present invention. 4, the embodiment of the present invention, the amplifier is a four cascaded differential amplifiers, the composition of the four differential amplifiers is cascaded: a first stage comprising a first differential amplifier 301, resistor R _al, resistors R _bl, resistor R _all, the resistance R _bll, capacitance and the capacitance C _u; a terminating resistor R _al believe that the other end of the positive signal input port AINP, the other end of the resistor R _bl, resistors R _bl first differential amplifier 301 is inverted an output terminal, a resistor R _al resistors R _bl and contacts connected to the first differential amplifier 301 with one end to the inverting input terminal AINN signal input port, a parallel capacitor and resistor R _bl, R _all the resistor, the other end of the resistor R _bll , the other end of the resistor R _bll first differential amplifier 301 with the output terminal, a resistor and the resistor R _all access points ₁ ¾11 inverting input of a first differential amplifier 301, the capacitor C _u in parallel with the resistor R _bll; first The second stage includes a second differential amplifier 302, a resistor R _a2 , a resistor R _b2 , a resistor R _a21 , a resistor R _b21 , a capacitor C ₂ and a capacitor C ₂₁ ; one end of the capacitor C ₂ is connected to the opposite output end of the first differential amplifier 301, The other termination resistor R _{a 2} , the other end of the resistor R _a2 is connected to the non-inverting input end of the second differential amplifier 302, and the resistor R _{b2 is} connected between the inverting input end and the non-inverting output end of the second differential amplifier 302, one end of the capacitor C ₂₁ Connected to the non-inverting output of the first differential amplifier 301, the other end is connected to the resistor R _a21 , the other end of the resistor ₂₁ is connected to the inverting input of the second differential amplifier 302, and the resistor R _{b21 is} connected to the inverting input of the second differential amplifier 302. The third stage includes a third differential amplifier 303, a resistor R _a3 , a resistor R _b3 , a resistor R _a31 , a resistor R _b31 , a capacitor C _{3 ,} and a capacitor C ₃₁ ; the resistor R _{a3 is} connected to the second Between the inverting output of the differential amplifier 302 and the non-inverting input of the third differential amplifier 303, the resistor 1 _3⁄43 and the capacitor C ₃ are connected in parallel between the non-inverting input and the inverting output of the third differential amplifier 303. R _{a31 is} connected between the non-inverting output of the second differential amplifier 302 and the inverting input of the third differential amplifier 303, and the resistor R _b31 and the capacitor C ₃₁ are connected in parallel at the inverting input and the same direction of the third differential amplifier 303. The fourth stage includes a fourth amplifier 304, a resistor R _a4 , a resistor R _M , a resistor R _a41 , a resistor R _M1 , a capacitor C ₄ and a capacitor C ₄₁ ; one end of the capacitor C ₄ is connected to the third differential amplifier 303 Inverting output, the other end Resistor R _a4, the inverting input of the other end of the resistor R _a4 is a fourth amplifier 304, a resistor ₁ ¾4 connected between the inverting input terminal and an output terminal of the fourth amplifier 304, a capacitor C one end of the third differential ₄₁ the input amplifier 303 with the other end to the same output terminal, the other end of the resistor R _a41, R _a41 resistance fourth terminal of amplifier 304, the resistor ₁ ¾41 connected between the input terminal and the ground with a fourth amplifier 304 .

The amplifier shown in Figure 4 is a fully differential programmable gain amplifier with low-pass and high-pass filtering. It is divided into four stages. The circuit in each block is one level, and AINP is the positive phase signal input port. AINP is the negative phase signal input port input port and Vout is the signal output port. The differential input-output operational amplifier 301 (that is, the first differential amplifier) is connected to a negative feedback feedback structure. The value of the resistor Ral is equal to the value of the resistor Rai l, the value of the resistor Rb1 is equal to the value of the resistor Rbl l , and the closed-loop gain is determined by Rbl. The ratio of Ral to Ral determines that the ratio of Rbl to Ral is adjustable. The first stage has a low-pass function. Capacitor C1 and resistor Rbl determine the low-pass cutoff frequency. The value of capacitor C1 is equal to the value of capacitor C11. Capacitor C2 has a blocking function, and the offset voltage of the first stage circuit is blocked from being transmitted to the second stage; the operational amplifier 302 (ie, the second differential amplifier) is connected to a negative feedback structure, and the value of the resistor Ra2 is equal to the value of the resistor Ra21. , the value of the resistor Rb2 is equal to the value of the resistor Rb21, and its closed loop gain Determined by the ratio of Rb2 and Ra2, the gain of the second stage is generally lower than the unity gain or gain, and the ratio of Rb2 and Ra2 is adjustable; the second stage has a high-pass function at the same time, the capacitor C2 and the resistor Ra2 determine the high-pass cutoff frequency, and the capacitor C2 The value is equal to the value of capacitor C21. The operational amplifier 303 (ie, the third differential amplifier) is connected to a resistor negative feedback structure, the closed loop gain is determined by the ratio of Rb3 and Ra 3, the ratio of Rb3 and Ra 3 is adjustable, the value of the resistor Ra 3 and the value of the resistor Ra 31 Equally, the value of the resistor Rb 3 is equal to the value of the resistor Rb31. The capacitor C4 has a blocking function, and the offset voltage of the front circuit is blocked to the last stage; the operational amplifier 304 (ie, the fourth amplifier) is connected to a double-ended signal to a single-ended signal structure with a low gain or unity gain. The offset voltage of the entire PGA (Programmab le Ga in Amp lifi er, programmable gain amplifier) is only the offset voltage of the last stage.

FIG. 5 is a structural diagram of another fully differential programmable gain amplifier according to an embodiment of the present invention. 5, the embodiment of the present invention, the amplifier is a four cascaded differential amplifiers, the composition of the four differential amplifiers is cascaded: a first stage comprising a first differential amplifier 301, resistor R _al, resistors R _bl, R _all resistors and the resistor R _bll; a terminating resistor R _al inverted output terminal of the positive-phase signal input port AINP, the other end of the resistor R _bl, the other end of the resistor R _bl first differential amplifier 301, and resistors R _al resistors R _bl contacts with the first differential amplifier 301 connected to one end of the inverted signal of the input port AINN input terminal, a resistor R _all, the other end of the resistor R _bll, the other end of the resistor R _bll first differential amplifier 301 The same output terminal, the contact of the resistor R _all and the resistor R _b11 is connected to the inverting input terminal of the first differential amplifier 301; the second stage includes the second differential amplifier 302, the resistor R _a2 , the resistor R _b2 , the resistor R _a21 , the resistor R _B21 , a resistor ε _ε1 , a resistor ε _ε11 , a capacitor d , a capacitor C ₂ , a capacitor C _{u ,} and a capacitor C ₂₁ ; the resistor, the capacitor C ₂ and the resistor R _a2 are sequentially connected in series to the inverting output of the first differential amplifier 301 and Second differential amplification 302 between the same direction between the input terminal, the capacitor (^ R _el connected between the resistor and the capacitance C ₂ of the node and ground, a resistor R _b2 connected to the same differential amplifier 302 to a second input terminal and the inverted output terminal The resistor R _c11 , the capacitor C ₂₁ and the resistor R _a21 are sequentially connected in series between the non-inverting output terminal of the first differential amplifier 301 and the inverting input terminal of the second differential amplifier 302, and the capacitor C _{u is} connected to the resistor and the capacitor C. Between the junction of ₂₁ and ground, a resistor R _{b21 is} connected between the inverting input terminal and the non-inverting output terminal of the second differential amplifier 302; The third stage includes a third differential amplifier 303, a resistor R _a3 , a resistor R _b3 , a resistor R _{a31 ,} and a resistor R _b31 ; one end of the resistor R _a3 is connected to the opposite output end of the second differential amplifier 302 , and the other end is connected to the resistor R _b3 . The other end of the resistor R _b3 is connected to the inverting output terminal of the third differential amplifier 303 , the contact of the resistor R _a3 and the resistor R _b3 is connected to the non-inverting input terminal of the third differential amplifier 303 , and one end of the resistor R _a31 is connected to the second differential amplifier 302 . The same output terminal, the other end is connected to the resistor R _b31 , the other end of the resistor R _b31 is connected to the same output end of the third differential amplifier 303 , and the contact of the resistor R ₃₁ and the resistor R _b31 is connected to the reverse input of the third differential amplifier 303 The fourth stage includes a fourth amplifier 304, a resistor R _a4 , a resistor R _b4 , a resistor R _a41 , a resistor R _b41 , and a resistor R. ₂ , the resistance R. ₂₁ , capacitor C ₃ , capacitor C ₄ , capacitor C ₃₁ and capacitor C ₄₁ ; resistor R. _{2. The} capacitor C ₄ and the resistor R _a4 are sequentially connected in series between the inverting output terminal of the third differential amplifier 303 and the inverting input terminal of the fourth amplifier 304, and the capacitor C _{3 is} connected to the resistor R. ₂ and the junction of the capacitor C ₄ and the ground, the resistor R _{b4 is} connected between the inverting input terminal and the output terminal of the fourth amplifier 304, the resistor R. ₂₁ , capacitor C ₄₁ and resistor R _a41 are sequentially connected in series between the non-inverting output of the third differential amplifier 303 and the non-inverting input of the fourth amplifier 304, and the capacitor C _{31 is} connected to the resistor R. Between ₂₁ and the junction of capacitor C ₄₁ and ground, resistor R _{b41 is} connected between the non-inverting input of fourth amplifier 304 and ground.

The amplifier shown in Figure 5 is also a programmable gain amplifier, the only difference from the structure of Figure 4 is that the low pass in Figure 4 is placed behind the first stage and after the third stage.

FIG. 6 is a structural diagram of still another fully differential programmable gain amplifier according to an embodiment of the present invention. 6, the embodiment of the present invention, a differential amplifier is a three-stage cascade amplifier, the composition of the three-stage cascade of differential amplifiers: a first stage includes a differential amplifier 401, resistor R _Al, R _BL resistance, resistance R _All , resistor R _bll , capacitor and capacitor C _u ; one end of the resistor R _al is connected to the positive _phase signal input port AINP, the other end is connected to the resistor R _bl , the other end of the resistor 1 _3⁄41 is connected to the inverting output terminal of the differential amplifier 401, the resistor R with one end to the signal input port AINN inverted input terminal, a capacitor connected in parallel with the resistor R _bl, R _all the resistor, the other end of the resistor R _bll, the other end of the resistor R _bll contacts connected resistors R _bl and _al differential amplifier 401 Connected to the non-inverting output of the differential amplifier 401, the junction of the resistor R _all and the resistor R _b11 is connected to the non-inverting input terminal of the differential amplifier 401, the capacitor C _{u is} connected in parallel with the resistor R _b11 ; the second stage includes a differential amplifier 402, Resistor R _a2 , resistor R _b2 , resistor R _a21 , resistor R _b21 , capacitor C ₂ , capacitor C ₃ , capacitor C ₂₁ and capacitor C ₃₁ ; capacitor C ₂ and resistor R _a2 are sequentially connected in series to the reverse output of differential amplifier 401 Between the terminal and the non-inverting input of the differential amplifier 402, the capacitor C ₃ and the resistor R _b2 are connected in parallel between the non-inverting input and the inverting output of the differential amplifier 402, and the capacitor C ₂₁ and the resistor R _a21 are sequentially connected in series to each other. Between the inverting output of the amplifier 401 and the non-inverting input of the differential amplifier 402, the capacitor C ₃₁ and the resistor R _b21 are connected in parallel between the non-inverting input and the inverting output of the differential amplifier 402; the third stage includes an amplifier 403 Resistor R _a3 , resistor R _b3 , resistor R _a31 , resistor R _b31 , capacitor C ₄ and capacitor C ₄₁ ; capacitor C ₄ and resistor R _a3 are sequentially connected in series at the opposite output of differential amplifier 402 and in the same direction of amplifier 403 Between the input terminals, a capacitor C ₄₁ and a resistor R _a31 are sequentially connected in series between the non-inverting output of the differential amplifier 402 and the inverting input of the amplifier 403, and the resistor R _{b3 is} connected to the non-inverting input and output of the amplifier 403. between the enlarged contact resistance R _b31 The inverting input terminal 403 and ground.

The amplifier shown in Figure 6 is also a programmable gain amplifier, the only difference from the structure of Figure 4 is the combination of the second and third stages of Figure 4 into the second stage of Figure 6.

Here, we give several examples of digital/analog converters.

Figure 7.1 is a structural diagram of a digital/analog converter in an embodiment of the present invention. As shown in Figure 7.1, in this embodiment, the digital/analog converter uses a current mode R2R DAC to convert digital to analog, and the output range is up to one-half of the power supply ground voltage. In accordance with the reference level requirements of the present invention, a corresponding high and low potential reference level can be generated using a corresponding connection.

Figure 7.2 is a structural diagram of another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.2, in this embodiment, the digital/analog converter uses the current mode R2R DAC to achieve digital to analog conversion. The difference from the DAC shown in Figure 7.1 is that the output range is not limited to two-division. A power supply ground voltage, and the common mode level is adjustable, as determined by the Vcom voltage value. The use of such a DAC in accordance with the present invention can reduce the design complexity of the reference level generating circuit.

Figure 7.3 is a structural diagram of still another digital/analog converter in the embodiment of the present invention. As shown in Figure 7.3, in this embodiment, the digital/analog converter implements digital to analog using a voltage mode R2R DAC. The conversion range is not limited to one-half of the power supply ground voltage. The use of such a DAC in accordance with the present invention can reduce the design complexity of the reference level generating circuit.

Figure 7.4 is a structural diagram of still another digital/analog converter in the embodiment of the present invention. As shown in Figure 7. 4, in this embodiment, the digital/analog converter uses the R2R network to implement digital-to-analog conversion. The output range is 2 times Vref, and the maximum can be the power supply ground voltage. According to the present invention, since such an electric circuit is reduced, the design complexity and power consumption of the reference level generating circuit can be reduced by reducing one amplifier.

Here, we also give examples of several comparators.

FIG. 8 is a structural diagram of a comparator according to an embodiment of the present invention. As shown in FIG. 8, in this embodiment, the comparator includes three NMOS transistors MnO, Mn1, Mn2, and two PMOS transistors Mp Mp2 , and an inverter. The PMOS transistor Mpl and the gate of the PMOS transistor Mp2 are connected to each other. The pole is connected to the power supply Vcc, the drain of the PMOS transistor Mpl is connected to the drain of the LV1, and the source of the NMOS transistor Mn1 and the NMOS transistor Mn2 are connected to the drain of the MOS transistor MnO. The pole is connected to the drain of the PMOS transistor Mp2, the source of the MOS transistor MnO is grounded to GND, the gate is connected to the bias voltage Vbn, the input terminal of the inverter is connected to the drain of the PMOS transistor Mp2, and the gate of the MOS transistor Mn2 is a comparator. The positive input terminal Vin+, the gate of the 匪OS tube Mn1 is the inverting input terminal Vin- of the comparator, and the output terminal of the inverter is the output terminal Vo of the comparator. The comparator shown in Figure 8 is used for the comparison of the high levels in the three pairs of comparators in Figure 2, namely the comparison of VG1 + , VG2+ and VM+. Since the MN OS is used as an input tube, it is possible to implement a high level comparison function.

Figure 9 is a structural diagram of another comparator in the embodiment of the present invention. As shown in FIG. 9, in this embodiment, the comparator includes three PMOS transistors MpO, Mp3, Mp4 and two NMOS transistors Mn3, Mn4 and an inverter. The source of the PMOS transistor MpO is connected to the power supply Vcc, and the gate. Connected to the bias voltage Vbp, the drain is connected to the source of the PMOS transistor Mp3 and the PMOS transistor Mp4, the drain of the PMOS transistor Mp3 is connected to the drain and the gate of the NM0S transistor Mn3, and the source of the MOS transistor Mn3 and the MOS transistor Mn4 is grounded. GND, the drain of the MN4 transistor Mn4 is connected to the drain of the PMOS transistor Mp4, the input terminal of the inverter is connected to the drain of the MOS transistor Mn4, and the gate of the PMOS transistor Mp4 is the positive input terminal of the comparator Vin+, the PMOS transistor Mp3 The gate of the comparator is the inverting input Vin- of the comparator, and the output of the inverter is the output of the comparator Vo. The comparator shown in Figure 9 is used The comparison of the low levels in the three pairs of comparators in Figure 2, namely VG1_, VG2 - and VM - is compared. Since PM0S is used as an input tube, it is possible to implement a low level comparison function.

FIG. 10.1 is a structural diagram of a first magnetic induction module according to an embodiment of the present invention. In Figure 10.1, the magnetic induction module is a differential magnetic induction line. The two outputs of the differential magnetic induction line 可以 can be directly connected to the two inputs of the low pass filter module.

Figure 10.2 is a structural diagram of a second magnetic induction module in the embodiment of the present invention. In Figure 10.2, the magnetic sensing module is a differential Hall device, and the two output terminals of the differential Hall device are connected to the two input terminals of the low-pass filter module through a DC blocking capacitor.

Figure 10.3 is a structural diagram of a third magnetic induction module in the embodiment of the present invention. In Figure 10.3, the magnetic sensing module is a differential Hall device. One output of the differential Hall device is connected to one input of the low-pass filter module through a DC blocking capacitor, and the other output of the differential Hall device is directly connected to the low pass. The other input of the filter module is connected.

Figure 10.4 is a structural diagram of a fourth magnetic induction module in the embodiment of the present invention. In Figure 10.4, the magnetic sensing module is a differential Hall device. The two outputs of the differential Hall device are directly connected to the two inputs of the low-pass filtering module.

Figure 10.5 is a structural diagram of a fifth magnetic induction module in the embodiment of the present invention. In Figure 10.5, the magnetic induction module is a differential giant magnetoresistive device. The two outputs of the differential giant magnetoresistive device are connected to the two inputs of the low-pass filter module through a DC blocking capacitor.

FIG. 10.6 is a structural diagram of a sixth magnetic induction module according to an embodiment of the present invention. In Figure 10.6, the magnetic induction module is a differential giant magnetoresistive device. One output of the differential giant magnetoresistive device is connected to one input of the low-pass filter module through a DC blocking capacitor, and the other output of the differential giant magnetoresistive device. The terminal is directly connected to the other input of the low pass filter module.

Figure 7 is a structural diagram of a seventh magnetic induction module in the embodiment of the present invention. In Figure 10.7, the magnetic induction module is a differential giant magnetoresistive device, and the two outputs of the differential giant magnetoresistive device are directly connected to the two inputs of the low-pass filter module. The differential analog front end device for low frequency signal detection and transmission system provided by the invention can reduce the interference of circuit noise and environmental noise on low frequency signal detection and low frequency signals received in the transmission system, thereby improving the low frequency alternating magnetic field distance Accuracy of detection and control.

Based on the aforementioned differential analog front end apparatus for low frequency signal detection and transmission systems, the present invention also proposes a low frequency signal detection method. FIG. 11 is a flowchart of a method for detecting a low frequency signal according to an embodiment of the present invention. As shown in FIG. 11, in the embodiment, the low frequency signal detecting method includes the following steps: Step 1101: measuring an amplitude value of the induced voltage after being amplified at different distances;

Through experimental means, the amplitude values of the induced voltage of the magnetic induction module and the magnetic field-transmitting card reader at different distances are amplified by the amplifier on different mobile phone terminals, and corresponding records are made. FIG. 12 is a schematic diagram showing the correspondence between the distance and the amplitude of the low frequency sensing signal by the magnetic induction module being placed into different mobile communication terminals according to an embodiment of the present invention.

Step 1102: Establish a correspondence table between voltage amplitude and distance;

The measurement data of multiple terminals is processed to obtain a correspondence table of voltage amplitude and distance, as shown in Table 1.

Correspondence relationship between amplitude value and distance of low frequency sensing signal Distance between mobile communication terminal and card reader (cm) Induced signal amplitude (dBmV)

1cm 52

2cm 47

3cm 40

4cm 36

5cm 30 6cm 26

7cm 21

8cm 17

9cm 11

10cm 8

14cm 5 Step 1103, entering the low frequency magnetic field data decoding process;

Step 1105, setting a digital-to-analog converter output level;

If the distance to be decoded is D2, look up the correspondence table between the amplitude value and the distance, and obtain the variation range of the signal corresponding to D2 from +A2 to -A2. The amplitude of most noise is measured as A3, and the power output to the comparator is set. Flat L3, L4, such that L3 should be greater than +A3, and less than +A2; L4 is less than -A3, and greater than -A2, that is, when the distance is less than D2, decoding is allowed, otherwise decoding is not allowed.

Step 1107, the comparator output signal is delayed;

Step 1109, decoding the processed signal;

The decoder decodes the logically processed signal according to the encoding format to obtain low frequency magnetic field data stream information. The decoder sets the digital glitch filter to perform glitch filtering on the input digital signal.

Step 1111, completing one-way communication of the low frequency magnetic field signal;

The decoded data is correlated and applied to complete the one-way communication function of the low frequency magnetic field signal. Step 1104, entering a distance control process;

Step 1106, setting a digital-to-analog converter output level;

If the distance to be controlled is D1, find the correspondence table between the amplitude value and the distance, and the signal change amplitude corresponding to D1 is +A1 to -A1, and the proportional threshold of the set 1 signal is R1. According to A1 and R1, the output is set to the comparator. The levels L1, L2 satisfy the period in which the output signal amplitude of the front-end device is greater than L1 or the percentage of time less than L2 is equal to R1, that is, if it is greater than R1, it enters the distance D1 of the required control, otherwise it does not enter the range. It is required to control the distance D1. Step 1108, the comparator output signal logic or processing;

When a paired comparator is used to obtain a digital signal for judging the distance between the card reader and the card, the pair of digital signals are operated as follows: Comparing the output signal of the input high comparison level comparator with the low After the output signal of the level comparator is inverted, the signal is ORed to obtain a digital signal for distance determination.

Step 1110: sampling the logically processed signal to obtain a 0, 1 data stream;

Step 1112: Perform statistics on 0 and 1 data by using a preset time window.

The length of the time window is preset, and the 0 and 1 data in the time window are counted, and the ratio of 1 is calculated.

Step 1114, step 1116, comparing the statistical result with the set signal threshold of the set 1 to complete the distance judgment and realize the distance control.

Fig. 13 is a schematic diagram showing the decoding process using the paired comparators using the magnetic field data low frequency signal detecting method in the embodiment of the present invention. As shown in Figure 13, AO is the output signal of the amplifier. Input Comparator High Comparison Level VG+, Low Comparison Level VG-Set according to the decoding distance and by looking up the correspondence table of amplitude value and distance. D02 is the output signal of the comparator that inputs the high compare level, and D03 is the inverted signal of the output of the comparator that inputs the low compare level. After the hysteresis processing, the digital signal is a hysteretic logic processed signal of the output signals D02 and DO3 of the comparator. A digital glitch filter can be set to glitch the input signal. The low-frequency magnetic field data stream information can be obtained by decoding the hysteresis-processed signal according to the encoding format.

FIG. 14 is a schematic diagram of a distance control process using a pair of comparators using a low frequency signal detection method according to an embodiment of the present invention. As shown in Figure 14, AO is the output signal of the amplifier. The amplitude varies from -A1 to +A1, and the corresponding distance is assumed to require the distance L to be controlled. First, the correspondence table of the amplitude value and the distance is searched for, and the signal amplitude value at the distance is obtained. Set the proportional threshold of the 1 signal to R1. According to R1, the setting of the high comparison level VG+ and the low comparison level VG- satisfies the time percentage of the front-end device output signal amplitude greater than VG+ or less than VG- in one cycle. Equal to Rl. The signal D04 is obtained or processed by the output signals D02 and D03 of the paired comparators, and the signal is sampled to obtain the sampled 0 and 1 data streams. In the figure, the dotted line box on the 0 and 1 data streams represents the preset time window. The length of the time window is set to be equal to one signal period. The 0 and 1 signals in the time window are counted, and the ratio of the 1 signal is obtained. The proportional threshold of the signal is compared. If it is greater than the proportional threshold, the sensing module is considered to be within the distance L; otherwise, the distance is not considered to be entered.

Figure 15 is a diagram showing the decoding process using a magnetic field data low frequency signal detecting method using a single comparator in an embodiment of the present invention. As shown in Figure 15, AO is the output signal of the amplifier. The comparison level of the input comparator VG is set to the amplifier input reference level. The output signal of the comparator is used directly as the decoded signal. A digital glitch filter can be set to glitch the input signal. The signal is decoded according to the encoding format to obtain low frequency magnetic field data stream information.

16 is a schematic diagram of a distance control process using a single comparator using a low frequency signal detection method in an embodiment of the present invention. As shown in Figure 16, AO is the output signal of the amplifier. The amplitude varies from -A1 to +A1, and the corresponding distance is assumed to require the distance L to be controlled. First, the correspondence table between the amplitude value and the distance is searched to obtain the signal amplitude value at the distance. Set the proportional threshold of the 1 signal to R1. According to R1, the setting of the comparison level VG satisfies that in a period, the percentage of time that the front-end device output signal amplitude is greater than VG is equal to R1. The output signal of the comparator is sampled to obtain the sampled 0, 1 data stream. In the figure, the dotted line box on the 0 and 1 data streams represents the preset time window. The length of the time window is set equal to one signal period. The 0 and 1 signals in the time window are counted, and the ratio of the 1 signal is obtained. The proportional threshold of the signal is compared. If it is greater than the proportional threshold, the sensing module is considered to be within the distance L; otherwise, the distance is not considered to be entered.

The six comparators in Fig. 3 can be configured to be used in three pairs, and simultaneously perform decoding, determination of multiple distances, distance intervals, and control. It can also be used independently as six separate comparators, and performs decoding, multiple distances, and distance interval judgment and control. Some of the comparators can also be used in pairs to perform decoding or distance, distance interval judgment and control; Use on site to perform decoding or distance and distance interval judgment and control.

In fact, the front-end device can configure one or more comparators as needed for distance determination and control of multiple distances, multiple distance intervals, and low-frequency magnetic field signal decoding.

The low frequency signal detecting method provided by the invention can reduce the interference of the circuit noise and the environmental noise on the low frequency signal detected and the low frequency signal received in the transmission system, thereby improving the accuracy of the low frequency alternating magnetic field distance detection and control.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

Claim

A differential analog front end apparatus for a low frequency signal detection and transmission system for use in a short range communication system, comprising: at least one magnetic induction module, at least one low pass filtering module, at least one amplifier, at least one digital/ An analog converter and at least one comparator, wherein the magnetic induction module, the low pass filter module, and the amplifier are sequentially connected, and an output end of the amplifier is connected to a forward input end of the comparator, and the digital/analog converter The output is coupled to an inverting input of the comparator, the amplifier being a differential amplifier.

2. The differential analog front end device for low frequency signal detection and transmission system according to claim 1, comprising a magnetic induction module, a low pass filtering module, an amplifier, two digital/analog converters and two a comparator, the magnetic induction module, the low-pass filter module, and the amplifier are sequentially connected, and the output ends of the amplifiers are respectively connected to the forward inputs of the two comparators, and the two digital/analog converters The two comparators form two paths, and the output end of the digital/analog converter in each path is connected to the inverting input end of the comparator, and each pair of upper and lower paths constitutes a pair, a pair.

3. The differential analog front end device for low frequency signal detection and transmission system according to claim 1, comprising a magnetic induction module, a low pass filtering module, an amplifier, six digital/analog converters and six Comparing, the output ends of the amplifiers are respectively connected to the forward inputs of the six comparators, and the six digital/analog converters and the six comparators form a six-way, digital/analog in each way The output of the converter is connected to the inverting input of the comparator, and each pair of upper and lower channels form a pair, a total of three pairs.

4. The differential analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the magnetic induction module is a differential magnetic induction coil, a differential Hall device or a differential giant magnetoresistive device.

5. Before differential simulation for low frequency signal detection and transmission system according to claim 4 The terminal device is characterized in that: the magnetic induction module is a differential magnetic induction coil, and the two output ends of the differential magnetic induction coil are directly connected to the two input ends of the low-pass filter module.

6. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 4, wherein the magnetic induction module is a differential Hall device, and two output ends of the differential Hall device are separated a straight capacitor is connected to the two input ends of the low pass filter module; or an output end of the differential Hall device is connected to one input end of the low pass filter module through a DC blocking capacitor, and the differential Hall device is further connected One output is directly connected to the other input of the low pass filter module; or the two outputs of the differential Hall device are directly connected to the two inputs of the low pass filter module.

The differential analog front end device for low frequency signal detection and transmission system according to claim 4, wherein the magnetic induction module is a differential giant magnetoresistive device, and two output ends of the differential giant magnetoresistive device Connecting to two input ends of the low pass filter module through a DC blocking capacitor; or an output terminal of the differential giant magnetoresistive device is connected to an input end of the low pass filter module through a DC blocking capacitor, The other output of the differential giant magnetoresistive device is directly connected to the other input of the low pass filter module; or the two outputs of the differential giant magnetoresistive device are directly connected to the two inputs of the low pass filter module Connected to the end.

8. The differential analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the amplifier is a single-stage differential amplifier or a multi-stage cascaded differential amplifier connected to a resistance negative feedback network.

9. The differential analog front end device for low frequency signal detection and transmission system according to claim 8, wherein the amplifier is a four-stage cascaded differential amplifier, and the four-stage cascaded differential amplifier is composed of:

The first stage comprises a first differential amplifier, a resistor R _al, R _bl resistance, resistance R _all, the resistance R _bll, capacitance and the capacitance C _u; is a termination resistor R _al AINP phase signal input port, the other end of the resistor R _bl , the other end of said inverted output terminal of the first resistor R _bl differential amplifier, a resistor and the resistor R _al R _bl contacts connected to said first differential amplifier with one end to the inverting input terminal AINN signal input port, a parallel capacitor and resistor R _bl, R _all the resistor, the other end of the resistor R _bll, the other end of the resistor R _bll Connected to the same output terminal of the first differential amplifier, the contact of the resistor R _all and the resistor R _b11 is connected to the inverting input terminal of the first differential amplifier, and the capacitor C _u is connected in parallel with the resistor R _b11 ;

The fourth stage includes a fourth amplifier, a resistor R _a4 , a resistor R _b4 , a resistor R _a41 , a resistor R _b41 , a capacitor C _{4 ,} and a capacitor C ₄₁ ; one end of the capacitor C ₄ is connected to an inverting output of the third differential amplifier, The other end is connected to the resistor R _a4 , the other end of the resistor R _a4 is connected to the inverting input end of the fourth amplifier, and the resistor R _{b4 is} connected between the inverting input terminal and the output end of the fourth amplifier, the capacitor C ₄₁ One end is connected to the same output end of the third differential amplifier, the other end is connected to the resistor R _a41 , the other end of the resistor R _a41 is connected to the same input end of the fourth amplifier, and the resistor R _{M1 is} connected to the fourth amplifier Between the input and the ground.

10. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 8, wherein said amplifier is a four-stage cascaded differential amplifier, and said four-stage cascaded differential amplifier The composition of the device is:

The second stage includes a second differential amplifier, a resistor R _a2 , a resistor R _b2 , a resistor R _a21 , a resistor R _b21 , a resistor ε _ε1 , a resistor R _ell , a capacitor d , a capacitor C ₂ , a capacitor C _{u ,} and a capacitor C ₂₁ ; The capacitor C ₂ and the resistor R _a2 are sequentially connected in series between the inverting output terminal of the first differential amplifier and the non-inverting input terminal of the second differential amplifier, and the capacitor is connected to the resistor R _el and the capacitor C ₂ . Between the ground and the ground, a resistor R _{b2 is} connected between the non-inverting input terminal and the inverting output terminal of the second differential amplifier, and a resistor Ren, a capacitor C ₂₁ and a resistor R _a21 are sequentially connected in series to the first differential amplifier. Between the non-inverting output terminal and the inverting input terminal of the second differential amplifier, a capacitor C _{u is} connected between the junction of the resistor and the capacitor C ₂₁ and the ground, and the resistor R _{b21 is} connected to the opposite of the second differential amplifier. Between the input terminal and the same output terminal;

The third stage includes a third differential amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _{a31 ,} and a resistor R _b31 ; one end of the resistor R _a3 is connected to the opposite output end of the second differential amplifier, and the other end is connected to the resistor R _b3 , The other end of the resistor R _b3 is connected to the inverting output end of the third differential amplifier, and the contact of the resistor R _a3 and the resistor R _b3 is connected to the non-inverting input end of the third differential amplifier, and one end of the resistor R _a31 is connected to the first The same output of the two differential amplifiers, the other end is connected to the resistor R _b31 , the other end of the resistor R _b31 is connected to the same output end of the third differential amplifier, and the junction of the resistor R ₃₁ and the resistor R _b31 is connected to the third differential The inverting input of the amplifier;

The fourth stage includes a fourth amplifier, a resistor R _a4 , a resistor R _b4 , a resistor R _a41 , a resistor R _b41 , a resistor R _c2 , and a resistor R. ₂₁ , capacitor C ₃ , capacitor C ₄ , capacitor C ₃₁ and capacitor C ₄₁ ; resistor R. ₂ , capacitor C ₄ and The resistor R _{a4 is} sequentially connected in series between the inverting output terminal of the third differential amplifier and the inverting input terminal of the fourth amplifier, and the capacitor C _{3 is} connected to the resistor R. ₂ and the junction of the capacitor C ₄ and the ground, the resistor R _{M is} connected between the inverting input terminal and the output terminal of the fourth amplifier, the resistor R. ₂₁ , a capacitor C ₄₁ and a resistor R _a41 are sequentially connected in series between the non-inverting output terminal of the third differential amplifier and the non-inverting input terminal of the fourth amplifier, and the capacitor C _{31 is} connected to the resistor R. Between the junction of ₂₁ and capacitor C ₄₁ and ground, a resistor R _{M1 is} coupled between the non-inverting input of the fourth amplifier and ground.

11. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 8, wherein said amplifier is a three-stage cascaded differential amplifier, and said three-stage cascaded differential amplifier has the following composition:

The first stage comprises a first differential amplifier, a resistor R _al, resistors R _bl, resistance R _all, the resistance R _bll, capacitance and the capacitance C _u; is a termination resistor R _al AINP phase signal input port, the other end of the resistor Rbi, the other end of said inverted output terminal of the first resistor R _BL differential amplifier, the resistor R and the resistor R _BL _Al contacts connected with said first differential amplifier input terminal, a capacitor connected in parallel with the resistor R _BL, the resistor R _all of a reverse signal input port AINN end, the other end of the resistor R _bll, the other end of the resistor R _bll with a first differential amplifier connected to said first contact output terminal, and a resistor R _all of the resistance R _bll a non-inverting input of a differential amplifier, the capacitor C _u being connected in parallel with the resistor R _b11 ;

The third stage includes a third amplifier, a resistor R _a3 , a resistor R _b3 , a resistor R _a31 , a resistor R _b31 , a capacitor C ₄ and a capacitor C ₄₁ ; the capacitor C ₄ and the resistor ₃ are sequentially connected in series to the opposite of the second differential amplifier Output to Between the terminal and the non-inverting input of the third amplifier, a capacitor C ₄₁ and a resistor R _a31 are sequentially connected in series between the non-inverting output of the second differential amplifier and the inverting input of the third amplifier The resistor R _{b3 is} connected between the non-inverting input terminal and the output terminal of the third amplifier, and the resistor R _{b31 is} connected between the inverting input terminal of the third amplifier and the ground.

12. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 1, wherein said digital/analog converter is a current mode R2R structure, and an output range of said digital/analog converter The maximum is one-half of the power ground voltage.

The differential analog front end device for a low frequency signal detecting and transmitting system according to claim 1, wherein the digital/analog converter is a current mode R2R structure, and an output range of the digital/analog converter It is not limited to one-half of the power supply ground voltage, and the common mode level can be adjusted.

The differential analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the digital/analog converter is a voltage mode R2R structure, and an output range of the digital/analog converter Not limited to one-half of the power supply ground voltage.

The differential analog front end device for low frequency signal detection and transmission system according to claim 1, wherein the digital/analog converter is an R2R network structure, and the output range of the digital/analog converter is large. To the power ground voltage.

16. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 1, wherein the comparator for comparing the high level comprises three 匪OS tubes MnO, Mnl, Mn2 and two PM0S tube Mpl, Mp2, and an inverter, PM0S tube Mpl and PM0S tube Mp2 are connected to the gate, the source is connected to the power supply Vcc, the drain of the PM0S tube Mpl is connected to the drain of the OS tube Mnl, and the LV tube Mn 1 and the source of the MN2 tube Mn2 are connected to the drain of the MNO tube MnO, the drain of the MN2 tube Mn2 is connected to the drain of the PM0S tube Mp2, the source of the MOS transistor MnO is grounded to GND, and the gate is connected to the bias voltage. Vbn, the input of the inverter is connected to the drain of the PM0S transistor Mp2, the gate of the MN2 transistor Mn2 is the positive input terminal Vin+ of the comparator, and the gate of the MN OS Mn1 is the reverse input terminal of the comparator Vin_, reverse Device The output is the output of the comparator Vo.

17. The differential analog front end apparatus for low frequency signal detection and transmission system according to claim 1, wherein the comparator for comparing the low level comprises three PMOS transistors MpO, Mp3, Mp4 and two MN OS Mn3, Mn4 and an inverter, the source of the PMOS transistor MpO is connected to the power supply Vcc, the gate is connected to the bias voltage Vbp, the drain is connected to the source of the PMOS transistor Mp 3 and the PMOS transistor Mp4, and the PMOS transistor Mp 3 The drain is connected to the drain and gate of the MOS transistor Mn3, the source of the MOS transistor Mn3 and the MOS transistor Mn4 is grounded to GND, the drain of the MOS transistor Mn4 is connected to the drain of the PMOS transistor Mp4, and the input terminal of the inverter The gate of the MOS transistor Mn4 is connected, the gate of the PMOS transistor Mp4 is the forward input terminal V in+ of the comparator, the gate of the PMOS transistor Mp 3 is the inverting input terminal V in- of the comparator, and the output terminal of the inverter is The output of the comparator Vo.

A low-frequency signal detecting method, the differential analog front-end device for a low-frequency signal detecting and transmitting system according to any one of claims 1 to 17, which comprises:

Step b, according to the need of decoding the low-frequency signal to transmit data and control the swipe distance, combined with the signal-to-noise ratio requirement, the hysteresis decision voltage threshold is formed by the bi-level threshold outputted by one or more pairs of digital-to-analog converters to determine the analog signal, The code stream information transmitted by the low-frequency magnetic field, or the single-level threshold outputted by one or more digital-to-analog converters forms a decision voltage threshold to determine the analog signal, and obtains the code stream information transmitted by the low-frequency magnetic field; The bi-level threshold of the digital-to-analog converter output forms a non-hysteresis decision voltage threshold to determine the analog signal, obtains the distance characteristic information transmitted by the low-frequency magnetic field, or forms a single-level threshold through one or more digital-to-analog converter outputs. The non-hysteresis decision voltage threshold determines the analog signal to obtain the distance characteristic information transmitted by the low frequency magnetic field; step c, samples the signal after the non-hysteresis decision condition, obtains a 0, 1 code stream sequence, and sets a signal proportional threshold. The code stream sequence is counted within the set time window length, when the 1 signal occupies the code stream When the sequence ratio reaches the preset proportional threshold, it is considered to enter the preset distance range, no Then, it is considered that the distance range is not entered; the signal sequence after the decision of the hysteresis decision condition is decoded, the code stream information of the low frequency magnetic field is extracted, and the one-way communication of the low frequency magnetic field signal is completed.

The low-frequency signal detecting method according to claim 18, wherein in the step b, according to the correspondence table of the voltage amplitude and the distance in the step a, the decoding distance, the distance control requirement, and the setting 1 are combined. The proportional threshold of the signal sets the level at which the digital-to-analog converter outputs to the comparator.

The low-frequency signal detecting method according to claim 19, wherein the level of the pair of digital-to-analog converters outputted to the comparator is a non-hysteresis decision condition, and the setting method is: setting the distance of the desired control to D1, find the correspondence table between the voltage amplitude and the distance, and obtain the signal variation range corresponding to the distance D1 from +A1 to -A1, and set the proportional threshold of the signal to R1. According to A1 and R1, set the level to the comparator L1. L2 is satisfied that within one cycle, the percentage of time that the analog front-end device output signal amplitude is greater than L1 or less than L2 is equal to R1, that is, if it is greater than R1, it enters the range of the required control distance D1, otherwise it does not enter the range of the required control distance D1.

The low-frequency signal detecting method according to claim 19, wherein the level of the pair of digital-to-analog converters outputted to the comparator is a hysteresis decision condition, and the setting method is: setting the distance at which decoding is desired to be D2, find the correspondence table of voltage amplitude and distance, and obtain the change range of the signal corresponding to the distance D2 from +A2 to -A2. The amplitude of most noise is measured as A3, and the level of output to the comparator is set to L3, L4. Let L3 be greater than +A3 and less than +A2; L4 is less than -A3 and greater than -A2, ie, decoding is allowed when the distance is less than D2, otherwise decoding is not allowed.

The low frequency signal detecting method according to claim 18, wherein in the step b, the two comparator output signals input to the Y hysteresis decision condition comparison level are logically ORed to obtain an extraction method. The digital signal of the distance information.

The low frequency signal detecting method according to claim 18, wherein in the step b, the two comparator outputs whose input is the hysteresis decision condition comparison level are subjected to hysteresis processing to obtain a magnetic field code stream. Digital signal of information.

The low frequency signal detecting method according to claim 18, wherein said step c The digital glitch filter is set to perform glitch filtering on the input digital signal, and the low frequency magnetic field data stream is decoded from the signal for filtering the glitch.

The low frequency signal detecting method according to claim 18, wherein in the step b, the comparison level extraction magnetic field distance information and the code stream information are output using a single comparator.

The low frequency signal detecting method according to claim 25, wherein the magnetic field stream information is extracted using a single comparison level output from a single digital to analog converter, and the level of the digital to analog converter output to the comparator is set to an amplifier. Enter the reference level.

The low frequency signal detecting method according to claim 18, wherein the decoding is performed using a digital signal output from a single comparator or a pair of comparators.

The low frequency signal detecting method according to claim 18, wherein a single distance is judged using a single comparator or a digital signal output from a pair of comparators; and the plurality of single comparator outputs are used to perform a plurality of signals Judgment of distance, or use multiple pairs of comparators to determine multiple distances and multiple distance intervals; use multiple digital comparator output digital signals to determine multiple distances, or use multiple pairs of comparators Judgment of multiple distances and multiple distance intervals.

The low-frequency signal detecting method according to claim 18, wherein the plurality of single comparators and the digital signals output from the paired comparators are mixed to determine a plurality of distances and a plurality of distance intervals.