WO2013067659A1 - Bump structure of wafer bonding pad and manufacturing method thereof - Google Patents

Bump structure of wafer bonding pad and manufacturing method thereof Download PDF

Info

Publication number
WO2013067659A1
WO2013067659A1 PCT/CN2011/001892 CN2011001892W WO2013067659A1 WO 2013067659 A1 WO2013067659 A1 WO 2013067659A1 CN 2011001892 W CN2011001892 W CN 2011001892W WO 2013067659 A1 WO2013067659 A1 WO 2013067659A1
Authority
WO
WIPO (PCT)
Prior art keywords
bumps
electroless
protective layer
layer
bump
Prior art date
Application number
PCT/CN2011/001892
Other languages
French (fr)
Chinese (zh)
Inventor
璩泽明
朱贵武
Original Assignee
Chu Tse-Ming
Chu Kuei-Wu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chu Tse-Ming, Chu Kuei-Wu filed Critical Chu Tse-Ming
Priority to PCT/CN2011/001892 priority Critical patent/WO2013067659A1/en
Publication of WO2013067659A1 publication Critical patent/WO2013067659A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13562—On the entire exposed surface of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A bump structure of a wafer bonding pad and manufacturing method thereof, the wafer comprising a surface with a plurality of bonding pads disposed thereon and a first protective layer formed thereon, the surface exposing a plurality of openings to the plurality of bonding pads. The method comprises: firstly, forming catalyst layers on the surface of the plurality of bonding pads exposed to the plurality of openings; then, forming bumps of an appropriate height on the surfaces of the plurality of catalyst layers in a photoresist or photoresist-free manner and in an electroless metal manner, the bumps being made of electroless nickel or electroless copper; stacking the plurality of bumps onto the plurality of bonding pads and a part of the first protective layer; furthermore, in an electroless gold manner, a second protective layer on the surface of the plurality of bumps is formed to prevent the bumps from being oxidized. The present invention forms the bumps of an appropriate height on the plurality of wafer bonding pads in an electroless nickel or electroless copper manner, thus simplifying manufacturing process and reducing manufacturing cost.

Description

晶圆焊垫的凸块结枸及其制造方法 技术领域 本发明涉及一种晶圓焊垫的凸块结构及其制造方法，尤指一种利 用无电解金属方式于晶圆的多个焊垫上形成适当高度且以无电解镍 或以无电解铜构成的凸块，以达成制造方法简化及制作成本降低的功 效。 背景技术  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump structure of a wafer pad and a method of fabricating the same, and more particularly to an electrode using a non-electrolytic metal on a plurality of pads of a wafer. A bump of an appropriate height and composed of electroless nickel or electroless copper is formed to achieve a simplification of the manufacturing method and a reduction in production cost. Background technique
在有关半导体晶片或晶圓的连结（如焊垫凸块）、封装（ package ) 或其相关制造方法的技术领域中， 目前已存在多种现有技术， 如： 中 国台湾 M397591、 M352128, M412460、 M412576、 M410659, 1306638、 1320588、 1255538、 1459362、 1253733、 1273651、 1288447、 1295498、 1241658、 1259572、 1472371、 1242866、 1269461、 1329917、 1282132、 1328266、 1284949; 及美国发明专利 US8，030,767、 US7,981，725、 US7,969，003、 US7,960,214、 US7,847,414、 US7,749,806、 US7，651,886、 US7,538,020、 US7,750,467 US7,364,944、 US7,019，406、 US6,507，120、 US7,999,387、 US7，993,967、 US7，868，470、 US7,868,449、 US7,972,902、 US7，960,825、 US7,952,187、 US7,944,043、 US7，934,313、 US7,906,855 等。 而经研读上述该多个背景技术的技术内容可知， 该多个专利几乎 都属于在其技术领域中微小的改进。换言之， 在有关半导体晶片或晶 圆的连结、封装或其相关制造方法的技术领域中， 其技术发展的空间 已相当有限， 因此在此技术发展空间有限的领域中（in the field of the crowded art ), 如能在技术上有^ 、的改进， 也得视为具有进步性， 仍能核准专利。  In the technical field related to the connection of semiconductor wafers or wafers (such as pad bumps), packages or related manufacturing methods, there are various existing technologies, such as: China Taiwan M397591, M352128, M412460, M412576, M410659, 1306638, 1320588, 1255538, 1459362, 1253733, 1273651, 1288447, 1295498, 1241658, 1259572, 1472371, 1242866, 1269461, 1329917, 1282132, 1328266, 1284949; and US invention patents US 8,030,767, US 7,981, 725, US 7,969,003, US 7,960,214, US 7,847,414, US 7,749,806, US 7,651,886, US 7,538,020, US 7,750,467 US 7,364,944, US 7,019,406, US 6,507,120, US 7,999,387 US 7,993,967, US 7,868,470, US 7,868,449, US 7,972,902, US 7,960,825, US 7,952,187, US 7,944,043, US 7,934,313, US 7,906,855, and the like. While studying the technical contents of the above various background technologies, it is known that the plurality of patents are almost all minor improvements in their technical fields. In other words, in the technical field of connection, packaging, or related manufacturing methods of semiconductor wafers or wafers, the space for technological development has been quite limited, and thus in the field where the development of the technology is limited (in the field of the crowded art) ), if there is technical improvement, it must be regarded as progressive, and patents can still be approved.
本发明的晶圆焊垫的凸块结构及其制造方法，在凸块结构及其制 造方法的技术发展空间有限的领域中，提出一种具有简化制造方法及 降低制作成本的功效的发明。由于上述该多个背景技术并未具体揭示 "利用无电解金属方式并配合有光阻或无光阻方式以在该多个焊垫 上形成一具适当高度且以无电解镍或无电解铜构成的凸块（bump )" 的技术手段，而且该多个背景技术在形成该多个凸块的前必须以凸块 底层金属化（Under Bump Metallization, UBM )制造方法在该多个焊 垫上先形成金属层，再以金属电镀或印刷银膏的方式在该多个焊垫的 金属层上形成该多个凸块， 因此， 该多个背景技术的制造方法不仅成 本较高且制作困难度也较高，而且相对地造成制造方法较复杂化及产 量降低， 况且该多个凸块需使用较多的贵金属材料， 故该多个背景技 术的制造方法难以符合实际使用时的需求。 The bump structure of the wafer pad of the present invention and the method of manufacturing the same have been proposed in the field of limited development of the bump structure and the manufacturing method thereof, and have an effect of simplifying the manufacturing method and reducing the manufacturing cost. Since the above plurality of background technologies do not specifically disclose "using an electroless metal method and being combined with a photoresist or no photoresist method for the plurality of pads A technical means of forming a bump of appropriate height and made of electroless nickel or electroless copper, and the plurality of background techniques must be metallized with a bump underneath before forming the plurality of bumps ( The under Bump Metallization (UBM) manufacturing method first forms a metal layer on the plurality of pads, and then forms the plurality of bumps on the metal layers of the plurality of pads by metal plating or printing silver paste, thereby The manufacturing method of the prior art is not only costly but also difficult to manufacture, and relatively complicated manufacturing methods and production yield reduction, and the plurality of bumps need to use more precious metal materials, so the plurality of backgrounds The manufacturing method of the technology is difficult to meet the needs in actual use.
由上可知， 在晶圆焊垫的凸块结构及其制造方法的技术领域中， 发展并设计一种制造方法简化、制作成本降低且符合效率要求的凸块 结构及其制造方法， 确实有其需要性。 本发明即针对上述该多个现有 技术的问题，提出解决的办法， 而且本发明不但揭示可具体实施的技 术手段， 且更具有简化制造方法及降低制作成本的功效增进， 因此本 发明应具有 "新颖性" 及 "创造性" 而能核准成为专利。 发明内容 本发明主要目的在于提供一种晶圆焊垫的凸块结构及其制造方 法， 其利用无电解金属方式， 并配合有光阻或无光阻方式， 以在该多 个焊垫上形成具有适当高度且以无电解镍或无电解铜构成的凸块 ( bump )， 以达成凸块制造方法筒化及制作成本降低的功效。  It can be seen from the above that in the technical field of the bump structure of the wafer pad and the manufacturing method thereof, a bump structure with a simplified manufacturing method, a reduced manufacturing cost, and an efficiency requirement, and a manufacturing method thereof are developed and designed. Needness. The present invention is directed to the above-mentioned problems of the prior art, and proposes a solution, and the present invention not only discloses the technical means that can be specifically implemented, but also has the effect of simplifying the manufacturing method and reducing the manufacturing cost, and therefore the present invention should have "novelty" and "creative" can be approved as patents. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a bump structure of a wafer pad and a method of fabricating the same, which utilizes an electroless metal method and is combined with a photoresist or a photoresist to form a plurality of pads on the plurality of pads. A bump (belt) of appropriate height and made of electroless nickel or electroless copper is used to achieve the effect of reducing the cost of the bump manufacturing method.
为实现上述目的， 本发明釆用的技术方案包括：  In order to achieve the above object, the technical solutions adopted by the present invention include:
一种晶圆焊垫的凸块结构， 其特征在于， 包括：  A bump structure of a wafer pad, characterized by comprising:
晶圆， 包括： 表面； 多个焊垫，设在该表面； 及一个第一保护层， 形成于该表面上并设有多个开口供对应显露该多个焊垫；  The wafer includes: a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads;
多个触媒层，其利用锌化处理以在该多个焊垫的表面上形成以锌 构成的触媒层； 及  a plurality of catalyst layers, which are zinced to form a catalyst layer made of zinc on the surface of the plurality of pads;
多个凸块， 其利用无电解镍或无电解铜的无电解金属方式， 并配 合有光阻或无光阻方式，以在该多个焊垫表面的该多个触媒层的表面 形成具由适当高度且以无电解镍或以无电解铜构成的凸块。 该多个凸块的表面上进一步设有一个第二保护层，用来防止该凸 块氧化； a plurality of bumps, which are made of electroless metal or electroless copper, and which are combined with a photoresist or a photoresist to form a surface of the plurality of catalyst layers on the surface of the plurality of pads A bump of appropriate height and consisting of electroless nickel or electroless copper. Further, a surface of the plurality of bumps is further provided with a second protective layer for preventing the bump from being oxidized;
其中当该多个凸块是以无电解镍构成时，该第二保护层利用无电 解金方式以在该多个凸块的表面上形成以无电解金构成的第二保护 层；  Wherein when the plurality of bumps are composed of electroless nickel, the second protective layer utilizes an electroless gold method to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当该多个凸块是以无电解铜构成时，该第二保护层先利用无 电解镍方式以在该多个凸块的表面上先形成以无电解镍构成的第二 保护层的底层，再利用无电解金方式以在该多个第二保护层的底层的 表面上再形成以无电解金构成的第二保护层的表层。  Wherein when the plurality of bumps are made of electroless copper, the second protective layer first uses an electroless nickel method to form a bottom layer of a second protective layer made of electroless nickel on the surfaces of the plurality of bumps. And using an electroless gold method to further form a surface layer of the second protective layer made of electroless gold on the surface of the underlayer of the plurality of second protective layers.
该触媒层是采用重量百分比浓度为 15-30 %的辞盐水溶液， 在溶 液温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。  The catalyst layer is a 15-30% by weight aqueous solution of salt water at a solution temperature of 20-35. The passage time in C is 10-60 seconds to form a catalyst layer composed of zinc.
该多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水 溶液， 在溶液温度 75-100 °C中经过时间 30-75分以沉积形成。  The plurality of bumps composed of electroless nickel are formed by depositing a nickel-salt solution having a concentration of 4-6.5 g/L at a solution temperature of 75-100 ° C for 30-75 minutes.
为实现上述目的， 本发明采用的技术方案还包括：  To achieve the above objective, the technical solution adopted by the present invention further includes:
一种晶圆焊垫的凸块制造方法， 其特征在于， 包括：  A method for manufacturing a bump of a wafer pad, comprising:
提供晶圆， 该晶圆具有表面； 多个焊垫， 设在该表面； 及一个第 一保护层， 形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用锌化处理以在该多个焊垫的表面形成以锌构成的触媒层；及 利用无电解镍或无电解铜方式以在该多个焊垫上的触媒层表面 上形成以无电解镍构成的凸块或以无电解铜构成的凸块。  Providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads; utilizing zincation Processing to form a catalyst layer made of zinc on the surface of the plurality of pads; and using electroless nickel or electroless copper to form bumps made of electroless nickel on the surface of the catalyst layer on the plurality of pads or A bump made of electroless copper.
在形成凸块的步骤之后进一步包含如下的步骤：再利用无电解金 属方式以在该多个凸块的表面上形成一个第二保护层；  After the step of forming the bumps, further comprising the steps of: reusing an electroless metal method to form a second protective layer on the surface of the plurality of bumps;
其中当该多个凸块是以无电解镍构成时，其利用无电解金方式以 在该多个凸块的表面上形成以无电解金构成的第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, they are formed by electroless gold to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当该多个凸块是以无电解铜构成时，其先利用无电解镍方式 以在该多个凸块的表面上先形成以无电解镍构成的第二保护层的底 层，再利用无电解金方式以在该多个第二保护层的底层的表面上再形 成以无电解金构成的第二保护层的表层。  Wherein, when the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by using an electroless nickel method. The electrolytic gold method forms a surface layer of a second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
该触媒层是采用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶 液温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。 该多个以无电解镍构成的凸块是釆用浓度为 4-6.5 g/L的镍盐水 溶液， 在溶液温度 75-100 °C中经过时间 30-75分以沉积形成。 The catalyst layer is a solution of a zinc salt aqueous solution having a concentration of 15-30% by weight, at a solution temperature of 20-35. The elapsed time in C is 10 to 60 seconds to form a catalyst layer composed of zinc. The plurality of bumps composed of electroless nickel are formed by using a nickel salt aqueous solution having a concentration of 4-6.5 g/L at a solution temperature of 75-100 ° C for 30-75 minutes to deposit.
该多个凸块的厚度为 2-15μπι。  The plurality of bumps have a thickness of 2-15 μm.
该多个开口之间的距离为大于 16μπι， 以避免所形成的该多个凸 块之间因太过接近而造成短路。  The distance between the plurality of openings is greater than 16 μm to prevent a short circuit caused by the too close proximity between the plurality of bumps formed.
为实现上述目的， 本发明采用的技术方案还包括：  To achieve the above objective, the technical solution adopted by the present invention further includes:
一种晶圆焊垫的凸块制造方法， 其特征在于， 包含：  A method for manufacturing a bump of a wafer pad, characterized in that it comprises:
提供晶圆， 该晶圓具有表面； 多个焊垫设在该表面； 及一个第一 保护层形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用锌化处理 , 以在该多个烊垫的表面形成以锌构成的触媒层； 形成光阻层在该第一保护层及该触媒层上；  Providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads; using zincation, Forming a catalyst layer made of zinc on the surface of the plurality of mattresses; forming a photoresist layer on the first protective layer and the catalyst layer;
图案化该光阻层，以形成多个开口供分别对应显露各触媒层及各 触媒层的周围一部分的第一保护层； 及  Patterning the photoresist layer to form a plurality of openings for respectively exposing the first protective layer of each of the catalyst layers and a portion of each of the catalyst layers;
利用无电解镍或无电解铜方式，以在该多个开口中形成以无电解 镍构成的凸块或以无电解铜构成的凸块；  Utilizing electroless nickel or electroless copper to form bumps made of electroless nickel or bumps made of electroless copper in the plurality of openings;
移除该光阻层， 以显露该第二保护层、该多个凸块及该多个凸块 下方以外的该第一保护层。  The photoresist layer is removed to expose the second protective layer, the plurality of bumps, and the first protective layer other than below the plurality of bumps.
其在移除该光阻层之前， 进一步包括如下的步骤： 再利用无电解 金属方式以在该多个凸块的表面上形成一个第二保护层；  Before the photoresist layer is removed, the method further includes the following steps: using an electroless metal method to form a second protective layer on the surface of the plurality of bumps;
其中当该多个凸块是以无电解镍构成时，其利用无电解金方式以 在该多个凸块的表面上形成以无电解金构成的第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, they are formed by electroless gold to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当该多个凸块是以无电解铜构成时，其先利用无电解镍方式 以在该多个凸块的表面上先形成以无电解镍构成的第二保护层的底 层，再利用无电解金方式以在该多个第二保护层的底层的表面上再形 成以无电解金构成的第二保护层的表层。  Wherein, when the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by using an electroless nickel method. The electrolytic gold method forms a surface layer of a second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
该触媒层是采用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶 液温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。  The catalyst layer is a zinc salt aqueous solution having a concentration of 15-30% by weight, at a solution temperature of 20-35. The passage time in C is 10-60 seconds to form a catalyst layer composed of zinc.
该多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水 溶液， 在溶液温度 75-100。C中经过时间 30-75分以沉积形成。  The plurality of bumps made of electroless nickel are a nickel brine solution having a concentration of 4-6.5 g/L at a solution temperature of 75-100. The time in C is 30-75 minutes to form a deposit.
该多个凸块的厚度大于或等于 6μπι。 该多个开口之间的距离小于或等于 16μιη。 The plurality of bumps have a thickness greater than or equal to 6 μm. The distance between the plurality of openings is less than or equal to 16 μm.
为实现上述目的， 本发明采用的技术方案还包括：  To achieve the above objective, the technical solution adopted by the present invention further includes:
一种晶圆焊垫的凸块结构， 其特征在于， 包括：  A bump structure of a wafer pad, characterized by comprising:
晶圆， 包括： 表面； 多个焊垫， 其设在该表面； 及一个第一保护 层， 其形成于该表面上并设有多个开口供对应显露该多个焊垫； 一个第一金属层，其利用凸块底层金属化方式以在该多个焊垫及 第一保护层的表面上形成一个第一金属层； 及  The wafer includes: a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads; a first metal a layer that utilizes a bump underlayer metallization to form a first metal layer on the surface of the plurality of pads and the first protective layer;
多个凸块， 其利用无电解镍或无电解铜的无电解金属方式， 并配 合有光阻方式，以在该多个焊垫表面的该第一金属层的表面形成具有 适当高度且以无电解镍构成的凸块或以无电解铜构成的凸块。  a plurality of bumps, which are made of electroless metal or electroless copper, and are provided with a photoresist pattern to form an appropriate height on the surface of the first metal layer on the surface of the plurality of pads A bump made of electrolytic nickel or a bump made of electroless copper.
该多个凸块的表面上进一步设有一个第二保护层，该第二保护层 利用无电解金方式以在该多个凸块的表面上形成以无电解金构成的 第二保护层用来防止该凸块氧化；  Further, a surface of the plurality of bumps is further provided with a second protective layer, wherein the second protective layer is formed by electroless gold to form a second protective layer made of electroless gold on the surface of the plurality of bumps. Preventing the bump from oxidizing;
其中当该多个凸块是以无电解镍构成时，该第二保护层利用无电 解金方式以在该多个凸块的表面上形成以无电解金构成的第二保护 层；  Wherein when the plurality of bumps are composed of electroless nickel, the second protective layer utilizes an electroless gold method to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当该多个凸块是以无电解铜构成时，该第二保护层先利用无 电解镍方式以在该多个凸块的表面上先形成以无电解镍构成的笫二 保护层的底层，再利用无电解金方式以在该多个第二保护层的底层的 表面上再形成以无电解金构成的第二保护层的表层。  Wherein, when the plurality of bumps are made of electroless copper, the second protective layer first uses an electroless nickel method to form a bottom layer of the second protective layer composed of electroless nickel on the surfaces of the plurality of bumps. And using an electroless gold method to further form a surface layer of the second protective layer made of electroless gold on the surface of the underlayer of the plurality of second protective layers.
该多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水 溶液， 在溶液温度 75-100。C中经过时间 30-75分以沉积形成。  The plurality of bumps made of electroless nickel are a nickel brine solution having a concentration of 4-6.5 g/L at a solution temperature of 75-100. The time in C is 30-75 minutes to form a deposit.
该多个凸块的厚度大于或等于 6μπι。  The plurality of bumps have a thickness greater than or equal to 6 μm.
为实现上述目的， 本发明采用的技术方案还包括：  To achieve the above objective, the technical solution adopted by the present invention further includes:
一种晶圓烊垫的凸块制造方法， 其特征在于， 包括：  A method for manufacturing a bump of a wafer pad, comprising:
提供晶圆， 该晶圆具有表面； 多个焊垫， 设在该表面； 及一个第 一保护层， 形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用凸块底层金属化方式，以在该多个焊垫及该第一保护层的表 面形成一个第一金属层；  Providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads; utilizing bumps a bottom metallization manner to form a first metal layer on the surface of the plurality of pads and the first protective layer;
在该第一金属层上形成光阻层； 图案化该光阻层，以形成多个开口供分别对应显露该多个焊垫及 该多个焊垫的周围一部分的第一金属层； Forming a photoresist layer on the first metal layer; Patterning the photoresist layer to form a plurality of openings for respectively correspondingly exposing the plurality of pads and a portion of the first metal layer of the plurality of pads;
利用无电解镍或无电解铜方式，以在该多个开口中形成以无电解 镍构成的凸块或以无电解铜构成的凸块； 及  Utilizing an electroless nickel or electroless copper method to form a bump made of electroless nickel or a bump made of electroless copper in the plurality of openings;
移除该光阻层及该光阻层下方的第一金属层，以显露该多个凸块 及该多个凸块下方以外的该第一保护层。  Removing the photoresist layer and the first metal layer under the photoresist layer to expose the plurality of bumps and the first protective layer other than below the plurality of bumps.
在移除该光阻层之前， 进一步包括如下的步驟： 再利用无电解金 属方式以在该多个凸块的表面上形成一个第二保护层；  Before removing the photoresist layer, further comprising the steps of: reusing an electroless metal method to form a second protective layer on the surface of the plurality of bumps;
其中当该多个凸块是以无电解镍构成时，其利用无电解金方式以 在该多个凸块的表面上形成以无电解金构成的第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, they are formed by electroless gold to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当该多个凸块是以无电解铜构成时，其先利用无电解镍方式 以在该多个凸块的表面上先形成以无电解镍构成的第二保护层的底 层，再利用无电解金方式以在该多个第二保护层的底层的表面上再形 成以无电解金构成的第二保护层的表层。  Wherein, when the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by using an electroless nickel method. The electrolytic gold method forms a surface layer of a second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
该多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水 溶液， 在溶液温度 75-100。C中经过时间 30-75分以沉积形成。  The plurality of bumps made of electroless nickel are a nickel brine solution having a concentration of 4-6.5 g/L at a solution temperature of 75-100. The time in C is 30-75 minutes to form a deposit.
该多个凸块的厚度大于或等于 6μιη。  The plurality of bumps have a thickness greater than or equal to 6 μm.
该多个开口之间的距离小于或等于 16μιη。  The distance between the plurality of openings is less than or equal to 16 μm.
与现有技术相比较， 本发明具有的有益效果是： 达成凸块制造方 法简化及制作成本降低的功效。 附图说明 图 1A是本发明基板焊垫的凸块结构第一实施例的截面示意图； 图 1B是本发明基板焊垫的凸块结构第二实施例的截面示意图； 图 2A-2D是图 1所示凸块结构的凸块制造方法一实施例的截面 示意图；  Compared with the prior art, the present invention has the beneficial effects of achieving the simplification of the bump manufacturing method and the reduction of the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic cross-sectional view showing a first embodiment of a bump structure of a substrate pad of the present invention; FIG. 1B is a schematic cross-sectional view showing a second embodiment of a bump structure of a substrate pad of the present invention; FIG. 2A to FIG. A schematic cross-sectional view of an embodiment of a bump manufacturing method of the illustrated bump structure;
图 3A-3G是图 1所示凸块结构的凸块制造方法另一实施例的截 面示意图；  3A-3G are schematic cross-sectional views showing another embodiment of a bump manufacturing method of the bump structure shown in Fig. 1;
图 4是本发明基板烊垫的凸块结构第三实施例的截面示意'图； 图 5A-5G是图 4所示凸块结构的凸块制造方法一实施例的截面 示意图。 附图标记说明： 晶圆焊垫的凸块结构 1、 2、 3; 晶圆 10; 表面 11 ; 焊垫 12; 第一保护层 13; 开口 14; 触媒层 20; 凸块 30; 第二 保护层 40; 底层 40a; 表层 40b; 光阻层 50; 开口 51 ; 第一金属层 60。 Figure 4 is a schematic cross-sectional view showing a third embodiment of the bump structure of the substrate mat of the present invention; 5A-5G are schematic cross-sectional views showing an embodiment of a bump manufacturing method of the bump structure shown in Fig. 4. DESCRIPTION OF REFERENCE NUMERALS: bump structure of wafer pad 1, 2, 3; wafer 10; surface 11; pad 12; first protective layer 13; opening 14; catalyst layer 20; bump 30; Layer 40; bottom layer 40a; surface layer 40b; photoresist layer 50; opening 51; first metal layer 60.
具体实施方式 为使本发明更加明确详实， 将本发明的结构、 制造方法及技术特 征， 配合下列图示详述如后： BEST MODE FOR CARRYING OUT THE INVENTION In order to make the present invention more clear and detailed, the structure, manufacturing method and technical features of the present invention are described in detail with the following figures:
参考图 1A所示， 其是本发明基板焊垫的凸块结构第一实施例的 截面示意图。本实施例的晶圆焊垫的凸块结构 1 ,至少包含： 晶圆 10、 多个触媒层 20及多个凸块 30; 且进一步可包含多个第二保护层 40。  Referring to Fig. 1A, there is shown a schematic cross-sectional view of a first embodiment of a bump structure of a substrate pad of the present invention. The bump structure 1 of the wafer pad of the present embodiment includes at least: a wafer 10, a plurality of catalyst layers 20 and a plurality of bumps 30; and further comprising a plurality of second protective layers 40.
该晶圆 10包含： 表面 11; 多个焊垫 12, 其设在该表面 11; 及 一个第一保护层 13， 其形成于该表面 11上并设有多个开口 14供对 应显露该多个焊垫 12。 该晶圆 10—般由晶圆制造厂提供， 其中多个 焊垫 12设在该表面 11上的布局 （layout )并不限制， 可随客户需要 而设计为各种阵列的排列方式。 其中该第一保护层 13—般是氮化物 材质。  The wafer 10 includes: a surface 11; a plurality of pads 12 disposed on the surface 11; and a first protective layer 13 formed on the surface 11 and provided with a plurality of openings 14 for correspondingly exposing the plurality of Solder pad 12. The wafer 10 is generally provided by a wafer manufacturer, and the layout of the plurality of pads 12 on the surface 11 is not limited, and can be arranged in various arrays according to customer needs. The first protective layer 13 is generally a nitride material.
该多个触媒层 20利用锌化处理（Zincating ) 以在该多个焊垫 12 的表面上形成以辞构成的触媒层 20。 该触媒层 20 利用锌化处理 ( Zincating )所构成的锌化层，其主要功能是用来连接该多个焊垫（ die pad ) 12， 并同时作为在进行后续的无电解金属方式时的沉积媒介层， 以形成以无电解镍或无电解铜构成的凸块（bump ) 30。 在本实施例 中， 该触媒层 20是釆用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶液温度 20-35 °C中经过时间 10-60秒 ( sec ) 以形成以锌构成的 触媒层。  The plurality of catalyst layers 20 are zinced to form a catalyst layer 20 composed of a plurality of layers on the surface of the plurality of pads 12. The catalyst layer 20 utilizes a zincation layer formed by zincation, the main function of which is to connect the plurality of die pads 12 and simultaneously serve as a deposition in the subsequent electroless metal mode. The dielectric layer is formed to form a bump 30 composed of electroless nickel or electroless copper. In this embodiment, the catalyst layer 20 is made of a zinc salt aqueous solution having a concentration of 15-30% by weight, and a 10-30 second (sec) time at a solution temperature of 20-35 ° C to form a zinc-containing solution. Catalyst layer.
该多个凸块 30 利用无电解镍 ( Electroless Nickel )或无电解铜 ( Electroless Copper ) 的无电解金属方式， 并配合有光阻或无光阻方 式，以在该多个焊垫 12表面的该多个触媒层 20的表面形成具有适当 高度且以无电解镍或无电解铜构成的凸块（bump ) 30。 在本实施例 中， 该多个凸块 30的形成厚度是由无电解镍沉积生成。 本实施例所 使用的镍盐材料中， 以磷酸列的镍材如磷酸镍为最佳， 因磷酸镍具有 自我催化反应的作用功能，可有效提高以无电解镍所沉积生成的凸块 30的厚度（高度）， 以达到设计所需的凸块 30的厚度。 在本实施例 中， 该多个以无电解镍构成的凸块 30是釆用浓度为 4-6.5 g/L (克 /公 升）的镍盐水溶液，在溶液温度 75-100。C中经过时间 30-75分（ min ) 以沉积形成。 The plurality of bumps 30 utilize electroless nickel (Electroless Nickel) or electroless copper (electroless copper) of an electroless metal, in combination with a photoresist or a photoresist, to form an appropriate height on the surface of the plurality of catalyst layers 20 on the surface of the plurality of pads 12, and to be electroless nickel or none A bump made of electrolytic copper 30. In the present embodiment, the thickness of the plurality of bumps 30 is formed by electroless nickel deposition. In the nickel salt material used in the present embodiment, a nickel material such as nickel phosphate in phosphoric acid is preferred, and since the nickel phosphate has a function of self-catalytic reaction, the bump 30 formed by electroless nickel deposition can be effectively improved. Thickness (height) to achieve the thickness of the bumps 30 required for the design. In the present embodiment, the plurality of bumps 30 made of electroless nickel are aqueous solutions of nickel salts having a concentration of 4-6.5 g/L (g/liter) at a solution temperature of 75-100. The elapsed time in C is 30-75 minutes (min) to form by deposition.
该多个第二保护层 40主要是利用无电解金（ Electroless Gold )方 式， 以在该多个凸块的表面上形成以无电解金构成的第二保护层 40。 该多个第二保护层 40主要是用来防止以无电解镍或无电解铜所构成 的凸块 30被氧化， 以确保封装时的电导通性。 在本实施例中， 由于 该多个凸块 30是以无电解镍构成，因此该多个第二保护层 40是采用 浓度为 0.5-1.5 g/L (克 /公升） 的金盐水溶液， 在溶液温度 70-100。C 中经过时间 5-25秒（sec ) 而沉积形成。  The plurality of second protective layers 40 are mainly made of an electroless gold to form a second protective layer 40 made of electroless gold on the surfaces of the plurality of bumps. The plurality of second protective layers 40 are mainly used to prevent the bumps 30 composed of electroless nickel or electroless copper from being oxidized to ensure electrical conductivity during packaging. In this embodiment, since the plurality of bumps 30 are made of electroless nickel, the plurality of second protective layers 40 are made of a gold salt aqueous solution having a concentration of 0.5-1.5 g/L (g/L). The solution temperature is 70-100. The deposition time is 5-25 seconds (sec) in C.
此外， 参考图 1B所示， 其是本发明基板焊垫的凸块结构第二实 施例的截面示意图。 本实施例的晶圆焊垫的凸块结构 2与图 1A所示 第一实施例的晶圆焊垫的凸块结构 1大体相同，两实施例之间的主要 不同点在于： 第一实施例的该多个凸块 30是以无电解镍构成， 但本 第二实施例的该多个凸块 30是以无电解铜构成。当该多个凸块 30是 以无电解铜构成时， 由于无电解金若直接沉积在无电解铜上时，金与 铜会互相迁移， 导致失去无电解金的防止氧化功能， 故要先沉积一层 无电解镍来做为阻绝迁移层； 故本第二实施例的第二保护层 40是先 利用无电解镍（ Electroless Nickel )方式以在该多个凸块 30的表面上 先形成以无电解镍构成的第二保护层的底层 40a， 再利用无电解金 ( Electroless Gold )方式以在该多个第二保护层的底层 40a的表面上 再形成以无电解金构成的第二保护层的表层 40b,即当该多个凸块 30 是以无电解铜构成时， 该第二保护层 40则至少包含： 以无电解镍构 成的底层 40a及以无电解金构成的表层 40b。 Further, referring to FIG. 1B, which is a schematic cross-sectional view of a second embodiment of the bump structure of the substrate pad of the present invention. The bump structure 2 of the wafer pad of this embodiment is substantially the same as the bump structure 1 of the wafer pad of the first embodiment shown in FIG. 1A, and the main difference between the two embodiments is: The plurality of bumps 30 are made of electroless nickel, but the plurality of bumps 30 of the second embodiment are made of electroless copper. When the plurality of bumps 30 are made of electroless copper, since the electroless gold is directly deposited on the electroless copper, gold and copper migrate with each other, resulting in the loss of the electroless gold to prevent oxidation, so deposition is required first. A layer of electroless nickel is used as a barrier layer; therefore, the second protective layer 40 of the second embodiment is first formed on the surface of the plurality of bumps 30 by using an electroless nickel (electroless nickel) method. The bottom layer 40a of the second protective layer composed of electrolytic nickel is further formed by an electroless gold method to form a second protective layer composed of electroless gold on the surface of the bottom layer 40a of the plurality of second protective layers. The surface layer 40b, that is, when the plurality of bumps 30 are made of electroless copper, the second protective layer 40 comprises at least: an electroless nickel structure The bottom layer 40a and the surface layer 40b made of electroless gold.
由于该多个凸块 30在形成制造方法中， 可选择配合无光阻方式 或有光阻方式以在该多个焊垫 12表面的该多个触媒层 20的表面形 成， 因此以无电解镍或无电解铜构成的该多个凸块 30, 也因无光阻 方式或有光阻方式而可形成不同的高度；现分别说明无光阻方式或有 光阻方式的凸块制造方法如下：  Since the plurality of bumps 30 are formed in the manufacturing method, the photoresist may be selectively formed in a non-resistive manner or a photoresist manner to form on the surface of the plurality of catalyst layers 20 on the surface of the plurality of pads 12, thereby using electroless nickel. The plurality of bumps 30 formed of the electroless copper may also be formed into different heights due to the non-resistive mode or the photoresist mode; the bump manufacturing method of the non-resistive mode or the photoresist mode is respectively described as follows:
参考图 2A-2D所示，其图 1A所示凸块结构的制造方法一实施例 (无光阻方式）的截面示意图； 本实施例是以无电解镍构成该多个凸 块为例说明但不限制。 本实施例的凸块制造方法包含下列步骤：  2A-2D, a cross-sectional view of a method for manufacturing a bump structure shown in FIG. 1A (a photoresist-free method); this embodiment is an example in which the plurality of bumps are formed by electroless nickel. not limited. The bump manufacturing method of this embodiment includes the following steps:
参考图 2A所示， 提供晶圓 10, 该晶圆 10具有表面 11、 多个焊 垫 12设在该表面 11及一个第一保护层 13形成于该表面 11上并设有 多个开口 14供对应显露该多个焊垫 12; 其中， 该多个开口之间的距 离以大于 16μιη (微米， Ιθ η )为优选， 用来避免后续所形成的该多 个凸块 30之间因太过接近而造成短路。  Referring to FIG. 2A, a wafer 10 having a surface 11 on which a plurality of pads 12 are disposed and a first protective layer 13 are formed on the surface 11 and a plurality of openings 14 are provided. Correspondingly, the plurality of pads 12 are exposed; wherein a distance between the plurality of openings is preferably greater than 16 μm (micrometers, Ιθ η ) to prevent the plurality of bumps 30 formed subsequently from being too close And caused a short circuit.
再参考图 2Β所示， 再利用锌化处理（Zincating ), 以在该多个焊 垫 12的表面形成以锌构成的触媒层 20; 在本实施例中， 该触媒层 20 是采用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶液温度 20-35 。C中经过时间 10-60秒（sec ) 以形成以锌构成的触媒层 20。  Referring again to FIG. 2A, zincation treatment is used to form a catalyst layer 20 made of zinc on the surface of the plurality of pads 12; in the embodiment, the catalyst layer 20 is in a concentration by weight. For 15-30% zinc salt aqueous solution, the solution temperature is 20-35. The elapsed time in C is 10-60 seconds (sec) to form a catalyst layer 20 composed of zinc.
再参考图 2C所示， 再利用无电解镍或无电解铜方式， 以在该多 个焊垫 12上的触媒层 20表面上形成以无电解镍或以无电解铜构成的 凸块 30; 在本实施例中， 该多个以无电解镍构成的凸块 30是采用浓 度为 4-6.5 g/L (克 /公升）的镍盐水溶液， 在溶液温度 75-100。C中经 过时间 30-75分（min ) 以沉积形成。 又本实施例中， 该多个以无电 解镍构成的凸块 30的厚度为 2-15μηι (微米， l(T6m )。 Referring again to FIG. 2C, an electroless nickel or electroless copper is used to form bumps 30 made of electroless nickel or electroless copper on the surface of the catalyst layer 20 on the plurality of pads 12; In the present embodiment, the plurality of bumps 30 made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L (g/liter) at a solution temperature of 75-100. The elapsed time in C is 30-75 minutes (min) to form by deposition. In still another embodiment, the plurality of bumps 30 made of electroless nickel have a thickness of 2-15 μm (micrometers, l (T 6 m )).
再参考图 2D所示， 再利用无电解金属如无电解金的方式， 以在 该多个凸块 30的表面上形成一个第二保护层 40; 在本实施例中， 由 于该多个凸块 30是以无电解镍构成，因此该多个第二保护层 40是采 用浓度为 0.5-1.5 g/L (克 /公升）的金盐水溶液，在溶液温度 70-100。C 中经过时间 5-25秒 ( sec ) 而沉积形成以无电解金构成的第二保护层 40。 进一步而言， 若该多个凸块 30是以无电解铜构成， 则本步骤在 形成该第二保护层 40 时， 参考图 1B 所示， 是先利用无电解镍 ( Electroless Nickel )方式以在该多个凸块 30的表面上先形成以无电 解镍构成的第二保护层的底层 40a, 再利用无电解金 （Electroless Gold )方式以在该多个第二保护层的底层 40a的表面上再形成以无电 解金构成的第二保护层的表层 40b, 即当该多个凸块 30是以无电解 铜构成时， 则该第二保护层 40包含： 以无电解镍构成的底层 40a及 以无电解金构成的表层 40b。 Referring again to FIG. 2D, an electroless metal such as electroless gold is used to form a second protective layer 40 on the surface of the plurality of bumps 30; in this embodiment, due to the plurality of bumps 30 is composed of electroless nickel, and therefore the plurality of second protective layers 40 are aqueous solutions of gold salts having a concentration of 0.5 to 1.5 g/L (g/liter) at a solution temperature of 70 to 100. A second protective layer 40 composed of electroless gold is deposited in C for 5-25 seconds (sec). Further, if the plurality of bumps 30 are made of electroless copper, this step is When the second protective layer 40 is formed, referring to FIG. 1B, an electroless nickel (EMC) method is first used to form a second protective layer made of electroless nickel on the surface of the plurality of bumps 30. The bottom layer 40a is further formed by an electroless gold (Electroless Gold) method to form a surface layer 40b of a second protective layer made of electroless gold on the surface of the bottom layer 40a of the plurality of second protective layers, that is, when the plurality of protrusions When the block 30 is made of electroless copper, the second protective layer 40 includes a bottom layer 40a made of electroless nickel and a surface layer 40b made of electroless gold.
再参考图 3A-3G所示，其图 1A所示凸块结构的凸块制造方法另 一实施例（有光阻方式）的截面示意图； 本实施例也是以无电解镍构 成该多个凸块为例说明但不限制。本实施例的凸块制造方法包括下列 步骤：  Referring again to FIGS. 3A-3G, there is shown a cross-sectional view of another embodiment of the bump manufacturing method of the bump structure shown in FIG. 1A (having a photoresist method); in this embodiment, the plurality of bumps are also formed by electroless nickel. As an example, it is not limited. The bump manufacturing method of this embodiment includes the following steps:
参考图 3A所示， 提供晶圆 10， 该晶圆 10具有表面 11、 多个焊 垫 12设在该表面 11及一个第一保护层 13形成于该表面 11上并设有 多个开口 14供对应显露该多个焊垫 12。 其中， 该多个开口之间的距 离为小于或等于 16μιη (微米， l(T6m )。 Referring to FIG. 3A, a wafer 10 having a surface 11 having a plurality of pads 12 disposed on the surface 11 and a first protective layer 13 formed on the surface 11 and having a plurality of openings 14 is provided. Correspondingly, the plurality of pads 12 are exposed. Wherein, the distance between the plurality of openings is less than or equal to 16 μm (micrometer, l (T 6 m )).
再参考图 3Β所示， 再利用锌化处理（Zincating ), 以在该多个焊 垫 12的表面形成以辞构成的触媒层 20; 该触媒层 20的形成条件与 图 2B所示步骤相同。  Referring again to Fig. 3A, zincation treatment is used to form a catalyst layer 20 composed of a plurality of layers on the surface of the plurality of pads 12; the formation conditions of the catalyst layer 20 are the same as those shown in Fig. 2B.
再参考图 3C所示， 再形成光阻层 50在该第一保护层 13及该触 媒层 20上。  Referring again to FIG. 3C, a photoresist layer 50 is formed on the first protective layer 13 and the catalyst layer 20.
再参考图 3D所示， 再图案化该光阻层 50, 以形成多个开口 51 供分别对应显露各触媒层 20及各触媒层 20的周围一部分的第一保护 层 13。  Referring again to FIG. 3D, the photoresist layer 50 is patterned to form a plurality of openings 51 for respectively exposing the first protective layer 13 of each of the catalyst layers 20 and a portion of each of the catalyst layers 20.
再参考图 3E所示， 再利用无电解镍或无电解铜方式， 以在该多 个开口 51中形成以无电解镍或以无电解铜构成的凸块 30; 在本实施 例中，该多个以无电解镍构成的凸块 30的厚度为大于或等于 6μπι(微 米， Ιθ η ) (即厚度 > 6μπι )。 一般而言， 本实施例（有光阻方式）所 形成的凸块 30高度通常是高于前述实施例 （无光阻方式）所形成的 凸块 30高度； 该以无电解镍构成的凸块 30的形成条件与图 2C所示 的步骤相同。 再参考图 3F 所示， 再利用无电解金方式， 以在该多个凸块 30 的顶面上形成一个第二保护层 40。 若该多个凸块 30是以无电解铜构 成， 则本步骤在形成该第二保护层 40 时， 是先利用无电解镍 解镍构成的第二保护层的底层 40a, 再利用无电解金 （Electroless Gold )方式以在该多个第二保护层的底层 40a的表面上再形成以无电 解金构成的第二保护层的表层 40b， 即当该多个凸块 30是以无电解 铜构成时， 则该第二保护层 40包含： 以无电解镍构成的底层 40a及 以无电解金构成的表层 40b。 Referring again to FIG. 3E, an electroless nickel or electroless copper is used to form bumps 30 made of electroless nickel or electroless copper in the plurality of openings 51. In this embodiment, the plurality The thickness of the bumps 30 made of electroless nickel is greater than or equal to 6 μm (micrometers, Ιθ η ) (i.e., thickness > 6 μm). In general, the height of the bumps 30 formed by the present embodiment (having a photoresist method) is generally higher than the height of the bumps 30 formed by the foregoing embodiment (without photoresist); the bumps made of electroless nickel The formation conditions of 30 are the same as those shown in Fig. 2C. Referring again to FIG. 3F, an electroless gold is used to form a second protective layer 40 on the top surface of the plurality of bumps 30. If the plurality of bumps 30 are made of electroless copper, in this step, when the second protective layer 40 is formed, the bottom layer 40a of the second protective layer made of nickel by electroless nickel is used first, and then the electroless gold is used. (Electroless Gold) way to form a surface layer 40b of a second protective layer made of electroless gold on the surface of the bottom layer 40a of the plurality of second protective layers, that is, when the plurality of bumps 30 are made of electroless copper In this case, the second protective layer 40 comprises: a bottom layer 40a made of electroless nickel and a surface layer 40b made of electroless gold.
再参考图 3G所示， 再移除该光阻层 50， 以显露该第二保护层 40、 该多个凸块 30及该多个凸块 30下方以外的该第一保护层 13。  Referring to FIG. 3G, the photoresist layer 50 is removed to expose the second protective layer 40, the plurality of bumps 30, and the first protective layer 13 other than the plurality of bumps 30.
再参考图 4所示，其是本发明基板焊垫的凸块结构第三实施例的 截面示意图。本实施例的晶圆焊垫的凸块结构 3 ,至少包含： 晶圆 10、 一个第一金属层 60、 多个凸块 30及多个第二保护层 40。  Referring again to Fig. 4, there is shown a cross-sectional view of a third embodiment of the bump structure of the substrate pad of the present invention. The bump structure 3 of the wafer pad of the embodiment includes at least: a wafer 10, a first metal layer 60, a plurality of bumps 30, and a plurality of second protective layers 40.
该晶圆 10包含： 表面 11 ; 多个焊垫 12， 其设在该表面 11 ; 及 一个第一保护层 13 , 其形成于该表面 11上并设有多个开口 14供对 应显露该多个烊垫 12。 该晶圆 10—般由晶圆制造厂提供， 其中多个 焊垫 12设在该表面 11上的布局 （layout )并不限制， 可随客户需要 而设计为各种阵列的排列方式。 其中该第一保护层 13—般是氮化物 材质。  The wafer 10 includes: a surface 11; a plurality of pads 12 disposed on the surface 11; and a first protective layer 13 formed on the surface 11 and provided with a plurality of openings 14 for correspondingly exposing the plurality of烊 pad 12. The wafer 10 is generally provided by a wafer manufacturer, and the layout of the plurality of pads 12 on the surface 11 is not limited, and can be arranged in various arrays according to customer needs. The first protective layer 13 is generally a nitride material.
该第一金属层 60 利用凸块底层金属化 （ Under Bump Metallization, UBM )方式， 以在该多个焊垫 12及第一保护层 13的 表面上形成一个第一金属层 60。 筒言之， 本第三实施例以该第一金 属层 60取代图 1A所示第一实施例中的触媒层 20。  The first metal layer 60 is formed by a under bump metallization (UBM) method to form a first metal layer 60 on the surfaces of the plurality of pads 12 and the first protective layer 13. In other words, the third embodiment replaces the catalyst layer 20 in the first embodiment shown in Fig. 1A with the first metal layer 60.
该多个凸块 30 利用无电解镍 ( Electroless Nickel )或无电解铜 The plurality of bumps 30 utilize electroless nickel (Electroless Nickel) or electroless copper
( Electroless Copper ) 的无电解金属方式， 并配合有光阻方式， 以在 该多个焊垫 12表面的该多个第一金属层 60的表面形成具有适当厚度Electroless copper (electroless copper) combined with a photoresist method to form an appropriate thickness on the surface of the plurality of first metal layers 60 on the surface of the plurality of pads 12
(高度）且以无电解镍或无电解铜构成的凸块（bump ) 30。 本第三 实施例如同图 1A所示的第一实施例， 该多个凸块 30的形成厚度主 要是由无电解镍或无电解铜所沉积生成。在本实施例中， 该多个以无 电解镍构成的凸块是采用浓度为 4-6.5 g/L (克 /公升）的镍盐水溶液， 在溶液温度 75-100。C中经过时间 30-75分（min )以沉积形成如同图 3E所示的步骤。 (height) and a bump 30 made of electroless nickel or electroless copper. In the third embodiment, as in the first embodiment shown in FIG. 1A, the thickness of the plurality of bumps 30 is mainly formed by deposition of electroless nickel or electroless copper. In this embodiment, the plurality of The bump made of electrolytic nickel is a nickel salt aqueous solution having a concentration of 4-6.5 g/L (g/L) at a solution temperature of 75-100. The elapsed time in C is 30-75 minutes (min) to form a step as shown in Fig. 3E.
该多个第二保护层 40利用无电解金（ Electroless Gold )方式， 以 在该多个凸块 30的表面上形成以无电解金构成的第二保护层 40, 该 第二保护层 40的形成请参考图 3F所示的步驟。  The plurality of second protective layers 40 are formed by an electroless gold method to form a second protective layer 40 composed of electroless gold on the surface of the plurality of bumps 30, and the second protective layer 40 is formed. Please refer to the steps shown in Figure 3F.
在此说明第三实施例的晶圆烊垫的凸块结构 3 的有光阻方式的 凸块制造方法， 参考图 5A-5G所示， 其图 4所示凸块结构的凸块制 造方法一实施例的截面示意图；本实施例也是以无电解镍构成该多个 凸块为例说明但不限制。 本实施例的凸块制造方法包括下列步骤： 参考图 5A所示， 提供晶圆 10, 该晶圆 10具有表面 11、 多个焊 垫 12设在该表面 11及一个第一保护层 13形成于该表面 11上并设有 多个开口 14供对应显露该多个焊垫 12 (此步骤如同图 3A所示的步 骤）。  Here, a method for manufacturing a bump having a photoresist structure of a bump structure 3 of a wafer pad of the third embodiment will be described. Referring to FIGS. 5A to 5G, a bump manufacturing method 1 of the bump structure shown in FIG. A schematic cross-sectional view of an embodiment; this embodiment also illustrates, but is not limited to, the plurality of bumps formed of electroless nickel. The bump manufacturing method of the present embodiment includes the following steps: Referring to FIG. 5A, a wafer 10 having a surface 11 on which a plurality of pads 12 are disposed and a first protective layer 13 are formed The surface 11 is provided with a plurality of openings 14 for correspondingly exposing the plurality of pads 12 (this step is as shown in Figure 3A).
再参考图 5B 所示， 再利用凸块底层金属化 （Under Bump Metallization, UBM )方式， 以在该多个焊垫 12及该第一保护层 13 的表面形成一个第一金属层 60 (此步骤如同图 3A所示的步骤）。  Referring to FIG. 5B, an under bump metallization (UBM) method is further used to form a first metal layer 60 on the surface of the plurality of pads 12 and the first protective layer 13 (this step) As shown in Figure 3A).
再参考图 5C所示， 再形成光阻层 50在该第一金属层 60上（此 步骤如同图 3C所示的步骤）。  Referring again to Figure 5C, a photoresist layer 50 is formed over the first metal layer 60 (this step is as shown in Figure 3C).
参考图 5D所示， 再图案化该光阻层 50, 以形成多个开口 51供 分别对应显露该多个焊垫 12及该多个焊垫 12的周围一部分的第一金 属层 60 (此步驟如同图 3D所示的步骤）。  Referring to FIG. 5D, the photoresist layer 50 is patterned to form a plurality of openings 51 for respectively exposing the plurality of pads 12 and a portion of the periphery of the plurality of pads 12 (this step). As shown in Figure 3D).
参考图 5E所示， 再利用无电解镍或无电解铜方式， 以在该多个 开口 51中形成以无电解镍或无电解铜构成的凸块 30 (此步骤如同图 3E所示的步骤）； 在本实施例中， 该以无电解镍构成的凸块 30的形 成条件与图 2C 所示步骤相同。 又该多个以无电解镍构成的凸块 30 的厚度为大于或等于 6μηι (微米， 10—6m ) (即厚度 > 6μιη )。 Referring to FIG. 5E, an electroless nickel or electroless copper is used to form bumps 30 made of electroless nickel or electroless copper in the plurality of openings 51 (this step is as shown in FIG. 3E). In the present embodiment, the formation conditions of the bumps 30 made of electroless nickel are the same as those shown in Fig. 2C. Further, the thickness of the plurality of bumps 30 made of electroless nickel is greater than or equal to 6 μm (micrometer, 10-6 m) (i.e., thickness > 6 μmη).
再参考图 5F 所示， 再利用无电解金方式， 以在该多个凸块 30 的顶面上形成一个第二保护层 40 (此步骤如同图 3F所示的步骤）。  Referring again to Fig. 5F, an electroless gold is used to form a second protective layer 40 on the top surface of the plurality of bumps 30 (this step is the same as the step shown in Fig. 3F).
参考图 5G所示， 再移除该光阻层 50及该光阻层 50下方的第一 金属层 60， 以显露该多个凸块 30及凸块 30上的第二保护层 40， 以 及该多个凸块 30下方以外的该第一保护层 13 (此步骤如同图 3G所 示的步骤）。 Referring to FIG. 5G, the photoresist layer 50 and the first layer under the photoresist layer 50 are removed. a metal layer 60 to expose the plurality of bumps 30 and the second protective layer 40 on the bumps 30, and the first protective layer 13 outside the plurality of bumps 30 (this step is as shown in FIG. 3G) ).
以上所示仅为本发明的优选实施例， 对本发明而言仅是说明性 的， 而非限制性的。 在本专业技术领域具通常知识人员理解， 在本发 明权利要求所限定的精神和范围内可对其进行许多改变， 修改， 甚至 等效的变更， 但都将落入本发明的保护范围内。  The above are only the preferred embodiments of the present invention, and are merely illustrative and not restrictive. It will be apparent to those skilled in the art that many changes, modifications, and equivalents are possible within the spirit and scope of the invention as defined by the appended claims.

Claims

权 利 要 求 Rights request
1、 一种晶圆焊垫的凸块结构， 其特征在于， 包括： A bump structure for a wafer pad, characterized by comprising:
晶圓， 其包括： 表面； 多个焊垫， 设在该表面； 及一个第一保护 层， 形成于该表面上并设有多个开口供对应显露该多个垾垫；  a wafer comprising: a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads;
多个触媒层，其利用锌化处理以在该多个焊垫的表面上形成以锌 构成的触媒层； 及  a plurality of catalyst layers, which are zinced to form a catalyst layer made of zinc on the surface of the plurality of pads;
多个凸块， 其利用无电解镍或无电解铜的无电解金属方式， 并配 合有光阻或无光阻方式，以在该多个焊垫表面的该多个触媒层的表面 形成具有适当高度且以无电解镍或以无电解铜构成的凸块。  a plurality of bumps, which are made of electroless metal or electroless copper, and which are combined with a photoresist or a photoresist, so as to form appropriate on the surface of the plurality of catalyst layers on the surface of the plurality of pads A bump made of electroless nickel or electroless copper.
2、 根据权利要求 1所述的晶圆焊垫的凸块结构， 其特征在于， 所述多个凸块的表面上进一步设有一个第二保护层，用来防止所述凸 块氧化；  2. The bump structure of a wafer pad according to claim 1, wherein a surface of the plurality of bumps is further provided with a second protective layer for preventing oxidation of the bump;
其中当所述多个凸块是以无电解镍构成时，所述第二保护层利用 无电解金方式以在所述多个凸块的表面上形成以无电解金构成的所 述第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, the second protective layer utilizes an electroless gold method to form the second protection composed of electroless gold on the surfaces of the plurality of bumps Floor;
其中当所述多个凸块是以无电解铜构成时，所述第二保护层先利 用无电解镍方式以在所述多个凸块的表面上先形成以无电解镍构成 的所述第二保护层的底层，再利用无电解金方式以在所述多个第二保 护层的底层的表面上再形成以无电解金构成的所述第二保护层的表 层。  Wherein, when the plurality of bumps are made of electroless copper, the second protective layer first uses an electroless nickel method to form the first layer of electroless nickel on the surface of the plurality of bumps. The underlayer of the second protective layer is further formed by electroless gold to form a surface layer of the second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
3、 根据权利要求 1所述的晶圆焊垫的凸块结构， 其特征在于， 所述触媒层是采用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶液 温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。  3. The bump structure of a wafer pad according to claim 1, wherein the catalyst layer is a zinc salt aqueous solution having a concentration by weight of 15-30%, and the solution temperature is 20-35. The passage time in C is 10-60 seconds to form a catalyst layer composed of zinc.
4、 根据权利要求 1所述的晶圆焊垫的凸块结构， 其特征在于： 所述多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水溶 液， 在溶液温度 75-100。C中经过时间 30-75分钟以沉积形成。  4. The bump structure of a wafer pad according to claim 1, wherein: the plurality of bumps made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L. The solution temperature is 75-100. The time elapsed in C was 30-75 minutes to form a deposit.
5、 一种晶圆焊垫的凸块制造方法， 其特征在于， 包括： 提供晶圓， 该晶圆具有表面； 多个焊垫， 设在该表面； 及一个第 一保护层， 形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用锌化处理以在所述多个烨垫的表面形成以锌构成的触媒层; 及 5. A bump manufacturing method for a wafer pad, comprising: providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the a plurality of openings are provided on the surface for correspondingly exposing the plurality of pads; Using a zincation treatment to form a catalyst layer composed of zinc on the surface of the plurality of mattresses; and
利用无电解镍或无电解铜方式以在所述多个焊垫上的所述触媒 层表面上形成以无电解镍构成的所述凸块或以无电解铜构成的所述 凸块。  The bumps made of electroless nickel or the bumps made of electroless copper are formed on the surface of the catalyst layer on the plurality of pads by electroless nickel or electroless copper.
6、 根据权利要求 5所述的晶圆焊垫的凸块制造方法， 其特征在 于， 在形成所述凸块的步骤之后进一步包括如下的步骤： 再利用无电 解金属方式以在所述多个凸块的表面上形成一个第二保护层；  The bump manufacturing method of a wafer pad according to claim 5, further comprising the following steps after the step of forming the bump: reusing an electroless metal method to Forming a second protective layer on the surface of the bump;
其中当所述多个凸块是以无电解镍构成时，其利用无电解金方式 以在所述多个凸块的表面上形成以无电解金构成的所述第二保护层； 其中当所述多个凸块是以无电解铜构成时，其先利用无电解镍方 式以在所述多个凸块的表面上先形成以无电解镍构成的所述第二保 护层的底层，再利用无电解金方式以在所述多个第二保护层的底层的 表面上再形成以无电解金构成的所述第二保护层的表层。  Wherein when the plurality of bumps are composed of electroless nickel, they utilize an electroless gold method to form the second protective layer composed of electroless gold on the surfaces of the plurality of bumps; When the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by an electroless nickel method, and reused. An electroless gold method forms a surface layer of the second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
7、 根据权利要求 5所述的晶圆焊垫的凸块制造方法， 其特征在 于， 所述触媒层是采用重量百分比浓度为 15-30 %的锌盐水溶液， 在 溶液温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。  7. The bump manufacturing method of a wafer pad according to claim 5, wherein the catalyst layer is a zinc salt aqueous solution having a concentration by weight of 15-30%, and the solution temperature is 20-35. The passage time in C is 10-60 seconds to form a catalyst layer composed of zinc.
8、 根据权利要求 5所述的晶圆焊垫的凸块制造方法， 其特征在 于， 所述多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐 水溶液， 在溶液温度 75-100。C中经过时间 30-75分钟以沉积形成。  The bump manufacturing method of a wafer pad according to claim 5, wherein the plurality of bumps made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L. At a solution temperature of 75-100. The time elapsed in C was 30-75 minutes to form a deposit.
9、 根据权利要求 5所述的晶圆焊垫的凸块制造方法， 其特征在 于， 所述多个凸块的厚度是 2-15μιη。  9. The bump manufacturing method of a wafer pad according to claim 5, wherein the plurality of bumps have a thickness of 2-15 μm.
10、根据权利要求 5所述的晶圆焊垫的凸块制造方法， 其特征在 于， 所述多个开口之间的距离大于 16μιη, 以避免所形成的所述多个 凸块之间因太过接近而造成短路。  The bump manufacturing method of a wafer pad according to claim 5, wherein a distance between the plurality of openings is greater than 16 μm to avoid the formation of the plurality of bumps between Short circuit caused by proximity.
11、 一种晶圆焊垫的凸块制造方法， 其特征在于， 包括： 提供晶圆， 该晶圆具有表面； 多个焊垫设在该表面； 及一个第一 保护层形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用锌化处理， 以在该多个焊垫的表面形成以锌构成的触媒层； 形成光阻层在该第一保护层及该触媒层上； 图案化该光阻层，以形成多个开口供分别对应显露各触媒层及各 触媒层的周围一部分的第一保护层； 及 11. A bump manufacturing method for a wafer pad, comprising: providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface And forming a plurality of openings for correspondingly exposing the plurality of solder pads; forming a catalyst layer made of zinc on the surface of the plurality of solder pads by using a zincation treatment; forming a photoresist layer on the first protective layer and the catalyst On the floor Patterning the photoresist layer to form a plurality of openings for respectively exposing the first protective layer of each of the catalyst layers and a portion of each of the catalyst layers;
. 利用无电解镍或无电解铜方式，以在该多个开口中形成以无电解 镍构成的凸块或以无电解铜构成的凸块；  Using electroless nickel or electroless copper to form bumps made of electroless nickel or bumps made of electroless copper in the plurality of openings;
移除该光阻层， 以显露该第二保护层、该多个凸块及该多个凸块 下方以外的该第一保护层。  The photoresist layer is removed to expose the second protective layer, the plurality of bumps, and the first protective layer other than below the plurality of bumps.
12、 根据权利要求 11所述的晶圆焊垫的凸块制造方法， 其特征 在于， 在移除所述光阻层之前， 进一步包括如下的步骤： 再利用无电 解金属方式以在所述多个凸块的表面上形成一个第二保护层；  The method for manufacturing a bump of a wafer pad according to claim 11, further comprising the steps of: using an electroless metal to re-use the photoresist layer before removing the photoresist layer; Forming a second protective layer on the surface of the bumps;
其中当所述多个凸块是以无电解镍构成时，其利用无电解金方式 以在所述多个凸块的表面上形成以无电解金构成的第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, they are formed by electroless gold to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当所述多个凸块是以无电解铜构成时，其先利用无电解镍方 式以在所述多个凸块的表面上先形成以无电解镍构成的第二保护层 的底层，再利用无电解金方式以在所述多个第二保护层的底层的表面 上再形成以无电解金构成的'第二保护层的表层。  Wherein when the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by using an electroless nickel method. An electroless gold method is used to form a surface layer of the 'second protective layer' composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
13、 根据权利要求 11所述的晶圓焊垫的凸块制造方法， 其特征 在于， 所述触媒层是釆用重量百分比浓度为 15-30 %的锌盐水溶液， 在溶液温度 20-35。C中经过时间 10-60秒以形成以锌构成的触媒层。  The bump manufacturing method of a wafer pad according to claim 11, wherein the catalyst layer is a zinc salt aqueous solution having a concentration of 15-30% by weight, and the solution temperature is 20-35. The passage time in C is 10-60 seconds to form a catalyst layer composed of zinc.
14、 根据权利要求 11所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍 盐水溶液，在溶液温度 75-100。C中经过时间 30-75分钟以沉积形成。  The bump manufacturing method of a wafer pad according to claim 11, wherein the plurality of bumps made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L. At a solution temperature of 75-100. The time elapsed in C was 30-75 minutes to form a deposit.
15、 根据权利要求 11所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个凸块的厚度大于或等于 6μπι。  The bump manufacturing method of a wafer pad according to claim 11, wherein the plurality of bumps have a thickness greater than or equal to 6 μm.
16、 根据权利要求 11所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个开口之间的距离小于或等于 16μπι。  The bump manufacturing method of a wafer pad according to claim 11, wherein a distance between the plurality of openings is less than or equal to 16 μm.
17、 一种晶圆焊垫的凸块结构， 其特征在于， 包括：  17. A bump structure for a wafer pad, characterized by comprising:
晶圓， 其包括： 表面； 多个焊垫， 其设在该表面； 及一个第一保 护层， 其形成于该表面上并设有多个开口供对应显露该多个悍垫； 一个第一金属层，其利用凸块底层金属化方式以在该多个焊垫及 该第一保护层的表面上形成一个第一金属层； 及 多个凸块， 其利用无电解镍或无电解铜的无电解金属方式， 并配 合有光阻方式，以在该多个悍垫表面的该第一金属层的表面形成具有 适当高度且以无电解镍构成的凸块或以无电解铜构成的凸块。 a wafer comprising: a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface and having a plurality of openings for correspondingly exposing the plurality of pads; a metal layer using a bump underlayer metallization to form a first metal layer on the plurality of pads and the surface of the first protective layer; a plurality of bumps, which are made of electroless metal or electroless copper, and are provided with a photoresist pattern to form an appropriate height on the surface of the first metal layer on the surface of the plurality of mats and A bump made of electrolytic nickel or a bump made of electroless copper.
18、根据权利要求 17所述的晶圓焊垫的凸块结构， 其特征在于， 所述多个凸块的表面上进一步设有一个第二保护层，该第二保护层利 用无电解金方式以在所述多个凸块的表面上形成以无电解金构成的 第二保护层用来防止所述凸块氧化；  The bump structure of the wafer pad according to claim 17, wherein a surface of the plurality of bumps is further provided with a second protective layer, and the second protective layer is formed by an electroless gold method. Forming a second protective layer made of electroless gold on the surface of the plurality of bumps to prevent oxidation of the bump;
其中当所述多个凸块是以无电解镍构成时，所述第二保护层利用 无电解金方式以在所述多个凸块的表面上形成以无电解金构成的第 二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, the second protective layer utilizes an electroless gold method to form a second protective layer composed of electroless gold on the surface of the plurality of bumps;
其中当所述多个凸块是以无电解铜构成时，所述第二保护层先利 用无电解镍方式以在所述多个凸块的表面上先形成以无电解镍构成 的所述第二保护层的底层，再利用无电解金方式以在所述多个第二保 护层的底层的表面上再形成以无电解金构成的所述第二保护层的表 层。  Wherein, when the plurality of bumps are made of electroless copper, the second protective layer first uses an electroless nickel method to form the first layer of electroless nickel on the surface of the plurality of bumps. The underlayer of the second protective layer is further formed by electroless gold to form a surface layer of the second protective layer composed of electroless gold on the surface of the underlayer of the plurality of second protective layers.
19、根据权利要求 18所述的晶圆焊垫的凸块结构， 其特征在于， 所述多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍盐水溶 液， 在溶液温度 75-100。C中经过时间 30-75分钟以沉积形成。  The bump structure of a wafer pad according to claim 18, wherein the plurality of bumps made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L. The solution temperature is 75-100. The time elapsed in C was 30-75 minutes to form a deposit.
20、根据权利要求 18所述的晶圆焊垫的凸块结构，其特征在于， 所述多个凸块的厚度大于或等于 6μπι。  The bump structure of a wafer pad according to claim 18, wherein the plurality of bumps have a thickness greater than or equal to 6 μm.
21、 一种晶圓焊垫的凸块制造方法， 其特征在于， 包括： 提供晶圆， 该晶圆具有表面； 多个焊垫， 设在该表面； 及一个第 一保护层， 形成于该表面上并设有多个开口供对应显露该多个焊垫； 利用凸块底层金属化方式，以在该多个焊垫及该第一保护层的表 面形成一个第一金属层；  21 . A bump manufacturing method for a wafer pad, comprising: providing a wafer having a surface; a plurality of pads disposed on the surface; and a first protective layer formed on the surface a plurality of openings are formed on the surface for correspondingly exposing the plurality of pads; using a bump underlayer metallization to form a first metal layer on the surface of the plurality of pads and the first protective layer;
在该第一金属层上形成光阻层；  Forming a photoresist layer on the first metal layer;
图案化该光阻层，以形成多个开口供分别对应显露该多个烊垫及 该多个焊垫的周围一部分的第一金属层；  Patterning the photoresist layer to form a plurality of openings for respectively correspondingly exposing the plurality of germanium pads and a first metal layer of a portion of the plurality of pads;
利用无电解镍或无电解铜方式，以在该多个开口中形成以无电解 镍构成的凸块或以无电解铜构成的凸块； 及 移除该光阻层及该光阻层下方的第一金属层，以显露该多个凸块 及该多个凸块下方以外的该第一保护层。 Using an electroless nickel or electroless copper method to form a bump made of electroless nickel or a bump made of electroless copper in the plurality of openings; Removing the photoresist layer and the first metal layer under the photoresist layer to expose the plurality of bumps and the first protective layer other than the plurality of bumps.
22、 根据权利要求 21所述的晶圆焊垫的凸块制造方法， 其特征 在于， 在移除该光阻层之前， 进一步包括如下的步骤： 再利用无电解 金属方式以在所述多个凸块的表面上形成一个第二保护层；  The method for manufacturing a bump of a wafer pad according to claim 21, further comprising the steps of: reusing an electroless metal to be used in the plurality of photoresist layers before removing the photoresist layer Forming a second protective layer on the surface of the bump;
其中当所述多个凸块是以无电解镍构成时，其利用无电解金方式 以在所述多个凸块的表面上形成以无电解金构成的第二保护层；  Wherein when the plurality of bumps are composed of electroless nickel, they are formed by electroless gold to form a second protective layer composed of electroless gold on the surfaces of the plurality of bumps;
其中当所述多个凸块是以无电解铜构成时，其先利用无电解镍方 式以在所述多个凸块的表面上先形成以无电解镍构成的第二保护层 的底层，再利用无电解金方式以在该多个第二保护层的底层的表面上 再形成以无电解金构成的第二保护层的表层。  Wherein when the plurality of bumps are made of electroless copper, the first layer of the second protective layer made of electroless nickel is first formed on the surface of the plurality of bumps by using an electroless nickel method. The surface layer of the second protective layer composed of electroless gold is further formed on the surface of the underlayer of the plurality of second protective layers by an electroless gold method.
23、 根据权利要求 22所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个以无电解镍构成的凸块是采用浓度为 4-6.5 g/L的镍 盐水溶液，在溶液温度 75-100 °C中经过时间 30-75分钟以沉积形成。  The bump manufacturing method of a wafer pad according to claim 22, wherein the plurality of bumps made of electroless nickel are a nickel salt aqueous solution having a concentration of 4-6.5 g/L. The formation was carried out by a deposition time of 30-75 minutes at a solution temperature of 75-100 °C.
24、 根据权利要求 22所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个凸块的厚度大于或等于 6μπι。  The bump manufacturing method of a wafer pad according to claim 22, wherein the plurality of bumps have a thickness greater than or equal to 6 μm.
25、 根据权利要求 22所述的晶圆焊垫的凸块制造方法， 其特征 在于， 所述多个开口之间的距离小于或等于 16μπι。  The bump manufacturing method of a wafer pad according to claim 22, wherein a distance between the plurality of openings is less than or equal to 16 μm.
PCT/CN2011/001892 2011-11-11 2011-11-11 Bump structure of wafer bonding pad and manufacturing method thereof WO2013067659A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/001892 WO2013067659A1 (en) 2011-11-11 2011-11-11 Bump structure of wafer bonding pad and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/001892 WO2013067659A1 (en) 2011-11-11 2011-11-11 Bump structure of wafer bonding pad and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2013067659A1 true WO2013067659A1 (en) 2013-05-16

Family

ID=48288425

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/001892 WO2013067659A1 (en) 2011-11-11 2011-11-11 Bump structure of wafer bonding pad and manufacturing method thereof

Country Status (1)

Country Link
WO (1) WO2013067659A1 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6319830B1 (en) * 1999-02-16 2001-11-20 Sharp Kabushiki Kaisha Process of fabricating semiconductor device
US20030080422A1 (en) * 2001-10-25 2003-05-01 Seiko Epson Corporation Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment
US20030107132A1 (en) * 2001-10-31 2003-06-12 Industrial Technology Research Institute Structure of the metal bumping on the input/output connector of a substrate or wafer and method for manufacturing the same
US6653235B2 (en) * 2001-05-16 2003-11-25 Industrial Technology Research Institute Fabricating process for forming multi-layered metal bumps by electroless plating
CN101106115A (en) * 2006-07-14 2008-01-16 富士通株式会社 Semiconductor device and method for manufacturing the same
US20090221142A1 (en) * 2006-05-01 2009-09-03 Panasonic Corporation Method of forming a metal bump on a semiconductor device
CN101582386A (en) * 2008-05-14 2009-11-18 俞宛伶 Method for forming metallic bump on semiconductor component and sealing semiconductor component
TW201022486A (en) * 2008-10-31 2010-06-16 Sharp Kk Plating treatment apparatus

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6319830B1 (en) * 1999-02-16 2001-11-20 Sharp Kabushiki Kaisha Process of fabricating semiconductor device
US6653235B2 (en) * 2001-05-16 2003-11-25 Industrial Technology Research Institute Fabricating process for forming multi-layered metal bumps by electroless plating
US20030080422A1 (en) * 2001-10-25 2003-05-01 Seiko Epson Corporation Semiconductor wafer, method of manufacturing semiconductor wafer having bumps, semiconductor chip having bumps and method of manufacturing the same, semiconductor device, circuit board, and electronic equipment
US20030107132A1 (en) * 2001-10-31 2003-06-12 Industrial Technology Research Institute Structure of the metal bumping on the input/output connector of a substrate or wafer and method for manufacturing the same
US20090221142A1 (en) * 2006-05-01 2009-09-03 Panasonic Corporation Method of forming a metal bump on a semiconductor device
CN101106115A (en) * 2006-07-14 2008-01-16 富士通株式会社 Semiconductor device and method for manufacturing the same
CN101582386A (en) * 2008-05-14 2009-11-18 俞宛伶 Method for forming metallic bump on semiconductor component and sealing semiconductor component
TW201022486A (en) * 2008-10-31 2010-06-16 Sharp Kk Plating treatment apparatus

Similar Documents

Publication Publication Date Title
JP4209178B2 (en) Electronic component mounting structure and manufacturing method thereof
TWI462237B (en) Wiring board manufacturing method, semiconductor device manufacturing method and wiring board
TWI495051B (en) Coreless package substrate and fabrication method thereof
JP6057681B2 (en) Wiring board and manufacturing method thereof
TWI437674B (en) Semiconductor substrate, package and device
TWI533380B (en) Package structure and manufacturing method thereof
TW201114000A (en) Package carrier, package structure and process of fabricating package carrier
TW201732903A (en) Semiconductor device structure and method for forming the same
TW201110842A (en) Solder pad structure for printed circuit boards and fabrication method thereof
JP2014067941A5 (en)
TW488052B (en) Manufacture process of bumps of double layers or more
JP2011014644A (en) Wiring board and manufacturing method thereof
US20140308780A1 (en) Fabrication method of semiconductor package
JP2008288607A (en) Method for manufacturing electronic parts packaging structure
WO2013067659A1 (en) Bump structure of wafer bonding pad and manufacturing method thereof
TWI455216B (en) Package method for quad flat no-lead package and its structure formedby
TWI379396B (en) Pre-plated leadframe having enhanced encapsulation adhesion
TW200304176A (en) Semiconductor device and manufacturing method thereof
TWM492524U (en) Diepad bump structure
WO2014005246A1 (en) Chemical nickel plating bump structure of wafer soldering pad and manufacturing method therefor
TW201320206A (en) Diepad bump structure and bumping process thereof
JP2020537343A (en) Die mounting surface copper layer with protective layer for microelectronic devices
JP5382889B2 (en) Manufacturing method of package structure
CN114481100B (en) Method for chemically plating metals with different thicknesses and packaging method of device
TWI401755B (en) Package method for quad flat no-lead package

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11875457

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11875457

Country of ref document: EP

Kind code of ref document: A1