WO2014098558A1 - A constant pulse width generator - Google Patents

A constant pulse width generator Download PDF

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Publication number
WO2014098558A1
WO2014098558A1 PCT/MY2013/000240 MY2013000240W WO2014098558A1 WO 2014098558 A1 WO2014098558 A1 WO 2014098558A1 MY 2013000240 W MY2013000240 W MY 2013000240W WO 2014098558 A1 WO2014098558 A1 WO 2014098558A1
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WIPO (PCT)
Prior art keywords
signal
signals
pulse
generator
pulse generator
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Application number
PCT/MY2013/000240
Other languages
French (fr)
Inventor
Hanif CHE LAH
Leong Son Wee
Rozita BORHAN
Original Assignee
Mimos Bhd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Mimos Bhd. filed Critical Mimos Bhd.
Publication of WO2014098558A1 publication Critical patent/WO2014098558A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Definitions

  • the present invention generally pertains to a pulse generator and a method for producing pulse, more particularly the present invention pertains to a constant pulse width generator and a method for producing constant pulse width signals.
  • US patent no. 3277395 discloses a circuit for producing an output signal during the period between the pulses of repeating time displaced pulse pairs and, more specifically, to a circuit of this type which provides a disenabling signal for a predetermined portion of the period between successive first occurring pulses of repeating pulse pairs.
  • US patent no. 6346823 discloses a pulse generator for providing a pulse signal with a constant pulse width, with an edge detection means, coupled between a node and a ground terminal that detects an edge of an external clock to set a node to a predetermined level.
  • US patent no. US 7205814 B2 discloses an apparatus for generating an internal pulse signal by means of a pulse generator when a frequency of an external clock signal is high, while uses the external clock signals as an internal clock signal directly when a frequency of the external clock signal is high.
  • US patent application no. 2010/0127749 Al discloses pulse generator circuit coupled to receive feedback from a node of an associated clock buffer circuit is shown. Also, the prior art further mentions that variations from one pulse generator to another, when implemented using small devices, may result in a corresponding variation in pulse widths from one pulse generator to another.
  • the preceding prior arts does not disclose or teach a pulse generator that is generates constant pulse width output signals regardless of amplitude, period and pulse width variations in the input signals, including analog input signals.
  • the present invention is aimed at addressing the aforementioned problems.
  • the objective of the present invention is to provide a pulse generator for producing a constant pulse width output signal, preferably used as reference input signals.
  • It is an object of the present invention to provide a pulse generator comprising an input for receiving signals, a signal detector for detecting signal levels, a frequency divider for dividing frequency of the signals, at least a signal generator for generating predetermined pulse width signals, at least an integrator for integrating the signals, and at least an output for providing constant pulse width signals.
  • It is a further object of the present invention to provide method for producing pulse by means of the pulse generator comprises the steps of receiving an input signal, generating a modified signal, dividing the modified signal, triggering a pulse signal of the divided signal at a rising edge, setting a predetermined pulse width for each divided signals, and combining the divided signals for producing an output signal. It is another further object of the present invention to provide a pulse generator, wherein the pulse generator produces a predetermined constant pulse width signals with that the signal detector further comprises at least a predetermined threshold for determining output signal levels, and responsive to the input signal.
  • the pulse generator in the present invention therefore provides a constant pulse width output signals regardless whether the input is an analog signal, or varying in amplitude, period and pulse width, or even if the input signals are distorted with noise.
  • FIG 1 illustrates the schematic representation of the pulse generator in accordance to the present invention.
  • FIG. 2 illustrates the circuit diagram of the pulse generator in accordance to the present invention.
  • FIG. 3 illustrates the input signal into the pulse generator in accordance to the present invention.
  • FIG. 4 illustrates the input and output signal waveforms of the signal detector in accordance to the present invention.
  • Figure 5 illustrates the circuit diagram of the frequency divider in accordance to the present invention.
  • Figure 6 illustrates the input and output signal waveforms of the frequency divider in accordance to the present invention.
  • Figure 7 illustrates the circuit diagram of the signal generator in accordance to the present invention.
  • FIG. 8 illustrates the input and output signal waveforms of the signal generator in accordance to the present invention.
  • Figure 9 illustrates the circuit diagram of the integrator as preferred in accordance to the present invention.
  • Figure 10 illustrates the input and output signal waveforms of the integrator in accordance to the present invention.
  • FIG 11 illustrates the process flow of the pulse generator in accordance to the present invention.
  • the figure illustrates a schematic representation of the pulse generator (100) in accordance to the present invention, wherein the pulse generator (100) comprises an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing frequency of the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.
  • the pulse generator (100) comprises an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing frequency of the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.
  • the frequency divider (13) is preferably connected to a compensator (21) for improving undesirable system parameters such as steady state error, resonant peak, and rise time, thus improving system response.
  • the signal generator (14) is preferably connected to a delaying means (22), whereby the signal received into the signal generator (14) is delayed for a predetermined period. It is shown in the figure that the divided signals from the frequency divider (12) are further processed in the signal generator (14) individually, and each signal is inputted into the integrator (15).
  • the preferred embodiment in the present invention produces a predetermined constant pulse width signals at the output (16), regardless of variations in the input (11) signals.
  • the variations of the signals can be caused by noise, irregular amplitudes or period, or even if the input (11) signals are analog signals by nature.
  • Figure 2 illustrates a basic circuit diagram of the pulse generator (100) in accordance to the present invention.
  • the circuit diagram is partitioned into sections of an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.
  • circuit construction for each section in the present invention should not be limiting, as various modification and different components can be used throughout the description of the invention, and also in practical use.
  • the signal detector (12) further comprises at least a predetermined threshold for determining output signal levels, and is used for generating clean output signal to remove noise and glitches in any variable incoming input (11) signal, in that the signal detector (12) outputs signal levels responsive to the input signals, of high, low, or a combination thereof.
  • the frequency divider (13) then receives the clean signal.
  • Figure 4 shows the input and output signal waveforms of the signal detector (12) in accordance to the present invention. It is shown at the top portion of the graph above that the waveform of the signal into the signal detector (12) is sinusoidal, representing an oscillation of irregular input signals.
  • the sinusoidal waveform represents the signal received by the input (1 1) of the pulse generator (100) in accordance to the present invention.
  • the sinusoidal waveform is to represent the input signal as shown in Figure 3, wherein the signal is affected by noise, and in another preferred embodiment of the present invention, the signal is distorted with varying amplitudes, periods and glitches.
  • Figure 5 shows enlarged view of the circuit diagram for the frequency divider (13).
  • the frequency divider (13) in the present invention is for the purpose of dividing an input frequency, preferably by two.
  • the frequency divider (13) in the present invention includes a D-type flip flop (110) for capturing an input value.
  • the input signal from the signal detector (12) is applied to the clock input of the D-type flip flop (110) which provides a transition of the logical state of the Q output to be equal to the logical state of the D input for the input signal transition from low to high.
  • a D-type flip flop typically has three terminals, which are the D input signal, a clock input signal for capturing the D input signal, and a Q output signal arising from operation of the input signals.
  • the frequency divider (13) further includes an inverter (115) for inputting back the inverted signal from the Q output into the D input, so that the Q output changes the logical state in response to the rising edge of the clock input signal. This results in an output signal with a frequency one half of the input signal from the signal detector (12).
  • the frequency divider (13) produces two output signals, and inverters (120, 125, 130) are sued to invert the output signal from the inverter (115).
  • the frequency divider technique is used to circumvent overlapping of the output signals.
  • Figure 6 illustrates the input and output signal waveforms of the frequency divider (13) in accordance to the present invention, wherein the top portion of the graph shows the waveform of the signal received from the signal detector (12), and the bottom portion of the graph shows the divided output waveforms, preferably two output signals produced by the frequency divider (13).
  • Figure 7 shows an enlarged view of the circuit diagram for the signal generator (14).
  • the signal generator (14) is connected to a delaying means (22), which is shown as the time-delay circuit (300) in Figure 7, and further connected to a NAND gate (320) and inverters (310, 330, 340, 350).
  • NAND gates are logic gates in electronics which produce an output that is false only if all its inputs are true.
  • the inverter (310) in the signal generator (14) is to generate an inverted signal received from the frequency divider (13). Then, the delaying means (22), or the time-delay circuit (300), is for delaying the inverted input signal from the inverter (310) for a predetermined time.
  • the NAND gate (320) then receives the input signal and the output of the time- delay circuit (300) to generate pulse signal.
  • the output pulse signal has a pulse width corresponding to the predetermined value of time.
  • the inverters (340, 350) are connected to the NAND gate (320) input in series as buffers.
  • Figure 8 illustrates the input and output signal waveforms of the signal generator (14) in accordance to the present invention, wherein the graph has four portions, and the top portion of the graph shows the waveform of the signal received from the signal divider
  • the waveform signals generated by the signal generator (14) are shown as train of pulses in Figure 8 to have a constant predetermined width.
  • Figure 9 shows an enlarged view of the circuit diagram for the integrator (15).
  • the integrator (15) in the present invention comprises an OR gate (200) and four inverters (205, 210, 215 and 220) which are connected in series.
  • the first input to the OR gate (200) is received from the output pulse generated by the first signal generator (14), while the second input to the OR gate (200) is received from the signal generator (14) as preferred in the present invention, and the output of the OR gate (200) serves as the output (16) of the pulse generator (100).
  • the inverters (205, 210, 215 and 220) are connected in series to the output (16) of the pulse generator (100), which serves as a circuit driver for the output (16) pulse.
  • OR gates are logic gates in electronics which produce an output that is true for any input that is true, and false only if all its inputs are false.
  • Figure 10 illustrates the input and output signal waveforms of the integrator in accordance to the present invention, wherein the top portions of the graph show the input waveform of the signal received from the signal divider (13), and the portion bottom most shows the output waveform of the integrator (15), which is the final constant output pulse width of the pulse generator (100).
  • Figure 11 illustrates the process flow of the pulse generator in accordance to the present invention.
  • the method for producing pulse by means of the pulse generator (100) as shown in the process flow of Figure 11 comprises the steps of initially the signal detector (12) receiving an input (11) signal, then, the signal detector (12) generates a modified signal which is the clean signal.
  • the modified signal is divided by the frequency divider (13), and the signal is split and phase shifted.
  • a pulse signal of the divided signal at a rising edge is then triggered, a predetermined pulse width for each divided signals is set at the signal generator (14).
  • the train of constant pulse width signals from each signal generator (14) is combined using the integrator (15) for producing an output (16) to external circuits.

Abstract

The present invention generally pertains to a pulse generator (100) and a method for producing pulse, more particularly the present invention pertains to a constant pulse width generator and a method for producing constant pulse width signals, wherein the pulse generator (100) comprises an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing frequency of the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.

Description

A CONSTANT PULSE WIDTH GENERATOR
TECHNICAL FIELD
The present invention generally pertains to a pulse generator and a method for producing pulse, more particularly the present invention pertains to a constant pulse width generator and a method for producing constant pulse width signals.
BACKGROUND OF INVENTION
Conventional pulse generator typically produces output signal pulses very dependent to the input signals. As a matter of fact, variations in the input signals caused by noise and imperfection of the input signal source usually affect the generated output pulse width. Whilst the non-constant width pulse is used as reference input source for other circuits, the reference input source may affect performance of the circuits or system.
There are several prior arts unveiled pulse generators for producing constant pulse width output signals. US patent no. 3277395 discloses a circuit for producing an output signal during the period between the pulses of repeating time displaced pulse pairs and, more specifically, to a circuit of this type which provides a disenabling signal for a predetermined portion of the period between successive first occurring pulses of repeating pulse pairs.
US patent no. 6346823 discloses a pulse generator for providing a pulse signal with a constant pulse width, with an edge detection means, coupled between a node and a ground terminal that detects an edge of an external clock to set a node to a predetermined level. US patent no. US 7205814 B2 discloses an apparatus for generating an internal pulse signal by means of a pulse generator when a frequency of an external clock signal is high, while uses the external clock signals as an internal clock signal directly when a frequency of the external clock signal is high. US patent application no. 2010/0127749 Al discloses pulse generator circuit coupled to receive feedback from a node of an associated clock buffer circuit is shown. Also, the prior art further mentions that variations from one pulse generator to another, when implemented using small devices, may result in a corresponding variation in pulse widths from one pulse generator to another.
The preceding prior arts however does not disclose or teach a pulse generator that is generates constant pulse width output signals regardless of amplitude, period and pulse width variations in the input signals, including analog input signals. The present invention is aimed at addressing the aforementioned problems.
SUMMARY OF INVENTION
The objective of the present invention is to provide a pulse generator for producing a constant pulse width output signal, preferably used as reference input signals.
It is an object of the present invention to provide a pulse generator comprising an input for receiving signals, a signal detector for detecting signal levels, a frequency divider for dividing frequency of the signals, at least a signal generator for generating predetermined pulse width signals, at least an integrator for integrating the signals, and at least an output for providing constant pulse width signals.
It is another object of the present invention to provide a pulse generator, wherein the frequency divider is for avoiding overlapping of the output pulse signals, and the signal generator is used for detecting a rising edge of an incoming signal regardless of pulse amplitude and pulse width variations.
It is a further object of the present invention to provide method for producing pulse by means of the pulse generator, comprises the steps of receiving an input signal, generating a modified signal, dividing the modified signal, triggering a pulse signal of the divided signal at a rising edge, setting a predetermined pulse width for each divided signals, and combining the divided signals for producing an output signal. It is another further object of the present invention to provide a pulse generator, wherein the pulse generator produces a predetermined constant pulse width signals with that the signal detector further comprises at least a predetermined threshold for determining output signal levels, and responsive to the input signal.
It is yet another object of the present invention to provide a pulse generator, wherein the signal generator and the integrator are connected to a delaying means for controlling the signal and providing a predetermined time delay.
The pulse generator in the present invention therefore provides a constant pulse width output signals regardless whether the input is an analog signal, or varying in amplitude, period and pulse width, or even if the input signals are distorted with noise.
BRIEF DESCRIPTION OF DRAWINGS
Figure 1 illustrates the schematic representation of the pulse generator in accordance to the present invention.
Figure 2 illustrates the circuit diagram of the pulse generator in accordance to the present invention.
Figure 3 illustrates the input signal into the pulse generator in accordance to the present invention.
Figure 4 illustrates the input and output signal waveforms of the signal detector in accordance to the present invention.
Figure 5 illustrates the circuit diagram of the frequency divider in accordance to the present invention.
Figure 6 illustrates the input and output signal waveforms of the frequency divider in accordance to the present invention. Figure 7 illustrates the circuit diagram of the signal generator in accordance to the present invention.
Figure 8 illustrates the input and output signal waveforms of the signal generator in accordance to the present invention.
Figure 9 illustrates the circuit diagram of the integrator as preferred in accordance to the present invention. Figure 10 illustrates the input and output signal waveforms of the integrator in accordance to the present invention.
Figure 11 illustrates the process flow of the pulse generator in accordance to the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS
Described below are preferred embodiments of the present invention with reference to the accompanying drawings. Each of the following preferred embodiments describes an example not limiting in any aspect.
Referring to Figure 1, the figure illustrates a schematic representation of the pulse generator (100) in accordance to the present invention, wherein the pulse generator (100) comprises an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing frequency of the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.
The frequency divider (13) is preferably connected to a compensator (21) for improving undesirable system parameters such as steady state error, resonant peak, and rise time, thus improving system response. The signal generator (14) is preferably connected to a delaying means (22), whereby the signal received into the signal generator (14) is delayed for a predetermined period. It is shown in the figure that the divided signals from the frequency divider (12) are further processed in the signal generator (14) individually, and each signal is inputted into the integrator (15).
The preferred embodiment in the present invention produces a predetermined constant pulse width signals at the output (16), regardless of variations in the input (11) signals. The variations of the signals can be caused by noise, irregular amplitudes or period, or even if the input (11) signals are analog signals by nature.
Referring now to Figure 1 and Figure 2, Figure 2 illustrates a basic circuit diagram of the pulse generator (100) in accordance to the present invention.
The circuit diagram is partitioned into sections of an input (11) for receiving signals, a signal detector (12) for detecting signal levels, a frequency divider (13) for dividing the signals, at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals, at least an integrator (15) for integrating the signals, and at least an output (16) for providing constant pulse width signals.
It should be appreciated that the circuit construction for each section in the present invention should not be limiting, as various modification and different components can be used throughout the description of the invention, and also in practical use.
The signal detector (12) further comprises at least a predetermined threshold for determining output signal levels, and is used for generating clean output signal to remove noise and glitches in any variable incoming input (11) signal, in that the signal detector (12) outputs signal levels responsive to the input signals, of high, low, or a combination thereof. The frequency divider (13) then receives the clean signal.
Referring now to Figure 2, Figure 3 and Figure 4, Figure 4 shows the input and output signal waveforms of the signal detector (12) in accordance to the present invention. It is shown at the top portion of the graph above that the waveform of the signal into the signal detector (12) is sinusoidal, representing an oscillation of irregular input signals. The sinusoidal waveform represents the signal received by the input (1 1) of the pulse generator (100) in accordance to the present invention. The sinusoidal waveform is to represent the input signal as shown in Figure 3, wherein the signal is affected by noise, and in another preferred embodiment of the present invention, the signal is distorted with varying amplitudes, periods and glitches.
The bottom portion of the graph shown in Figure 4, the figure shows the output waveform of the signal detector (12), whereby a desired clean output is produced with signal levels of high and low shown without noise and glitches.
Referring now to Figure 2, Figure 5 and Figure 6, Figure 5 shows enlarged view of the circuit diagram for the frequency divider (13).
The frequency divider (13) in the present invention is for the purpose of dividing an input frequency, preferably by two. The frequency divider (13) in the present invention includes a D-type flip flop (110) for capturing an input value. The input signal from the signal detector (12) is applied to the clock input of the D-type flip flop (110) which provides a transition of the logical state of the Q output to be equal to the logical state of the D input for the input signal transition from low to high. It will be apparent to a person skilled in the art that a D-type flip flop typically has three terminals, which are the D input signal, a clock input signal for capturing the D input signal, and a Q output signal arising from operation of the input signals.
The frequency divider (13) further includes an inverter (115) for inputting back the inverted signal from the Q output into the D input, so that the Q output changes the logical state in response to the rising edge of the clock input signal. This results in an output signal with a frequency one half of the input signal from the signal detector (12). The frequency divider (13) produces two output signals, and inverters (120, 125, 130) are sued to invert the output signal from the inverter (115). The frequency divider technique is used to circumvent overlapping of the output signals.
Figure 6 illustrates the input and output signal waveforms of the frequency divider (13) in accordance to the present invention, wherein the top portion of the graph shows the waveform of the signal received from the signal detector (12), and the bottom portion of the graph shows the divided output waveforms, preferably two output signals produced by the frequency divider (13). Referring now to Figure 2, Figure 7 and Figure 8, Figure 7 shows an enlarged view of the circuit diagram for the signal generator (14). There are at least a signal generator (14) constructed in a pair for the present invention to receive the divided signals from the frequency divider (13). The signal generator (14) in the present invention or known as the monostable circuit, or the one-shot with time-delay circuit (300), is for the purpose of producing a positive logic edge-trigger pulse width. The signal generator (14) is connected to a delaying means (22), which is shown as the time-delay circuit (300) in Figure 7, and further connected to a NAND gate (320) and inverters (310, 330, 340, 350). It will be apparent to a person skilled in the art in that NAND gates are logic gates in electronics which produce an output that is false only if all its inputs are true.
The inverter (310) in the signal generator (14) is to generate an inverted signal received from the frequency divider (13). Then, the delaying means (22), or the time-delay circuit (300), is for delaying the inverted input signal from the inverter (310) for a predetermined time. The NAND gate (320) then receives the input signal and the output of the time- delay circuit (300) to generate pulse signal. The output pulse signal has a pulse width corresponding to the predetermined value of time. Further, the inverters (340, 350) are connected to the NAND gate (320) input in series as buffers.
Figure 8 illustrates the input and output signal waveforms of the signal generator (14) in accordance to the present invention, wherein the graph has four portions, and the top portion of the graph shows the waveform of the signal received from the signal divider
(13) , and the portion below the top portion of the graph shows the output waveforms of the signal generator (14). Then, the graph repeats its order for the next signal generator
(14) for the second signals from the frequency divider (13). The waveform signals generated by the signal generator (14) are shown as train of pulses in Figure 8 to have a constant predetermined width.
Referring now to Figure 2, Figure 9 and Figure 10, Figure 9 shows an enlarged view of the circuit diagram for the integrator (15).
The integrator (15) in the present invention comprises an OR gate (200) and four inverters (205, 210, 215 and 220) which are connected in series. The first input to the OR gate (200) is received from the output pulse generated by the first signal generator (14), while the second input to the OR gate (200) is received from the signal generator (14) as preferred in the present invention, and the output of the OR gate (200) serves as the output (16) of the pulse generator (100). It is also shown the inverters (205, 210, 215 and 220) are connected in series to the output (16) of the pulse generator (100), which serves as a circuit driver for the output (16) pulse. It will be apparent to a person skilled in the art in that OR gates are logic gates in electronics which produce an output that is true for any input that is true, and false only if all its inputs are false.
Figure 10 illustrates the input and output signal waveforms of the integrator in accordance to the present invention, wherein the top portions of the graph show the input waveform of the signal received from the signal divider (13), and the portion bottom most shows the output waveform of the integrator (15), which is the final constant output pulse width of the pulse generator (100).
Referring now to Figure 3 and Figure 11, Figure 11 illustrates the process flow of the pulse generator in accordance to the present invention.
The method for producing pulse by means of the pulse generator (100) as shown in the process flow of Figure 11 comprises the steps of initially the signal detector (12) receiving an input (11) signal, then, the signal detector (12) generates a modified signal which is the clean signal. The modified signal is divided by the frequency divider (13), and the signal is split and phase shifted. A pulse signal of the divided signal at a rising edge is then triggered, a predetermined pulse width for each divided signals is set at the signal generator (14). Finally, the train of constant pulse width signals from each signal generator (14) is combined using the integrator (15) for producing an output (16) to external circuits.
In as much as the present invention is subject to many variations, modifications and changes in detail, it is intended that all matter contained in the foregoing description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

1. A pulse generator (100) comprising:
an input (11) for receiving signals;
a signal detector (12) for detecting signal levels;
a frequency divider (13) for dividing frequency of the signals; at least a signal generator (14) for generating predetermined pulse width signals from the frequency divided signals;
at least an integrator (15) for integrating the divided signals; and at least an output (16) for providing constant pulse width signals;
characterized in that the pulse generator (100) further comprises a delaying means (22) for instituting time delay of the signals; and
the pulse generator (100) produces constant output pulse width signals notwithstanding variations in the received input signals.
2. A pulse generator (100) in accordance to claim 1, wherein the pulse generator (100) produces a predetermined constant pulse width signal.
3. A pulse generator (100) in accordance to claim 1, wherein the signal detector (12) further comprises at least a predetermined threshold for determining output signal levels.
4. A pulse generator (100) in accordance to claim 1, wherein the signal detector (12) provides output signal levels responsive to the input signals, of high, low, or a combination thereof.
5. A pulse generator (100) in accordance to claim 1, wherein the frequency divider
(13) further comprises at least an electronic flip-flop, and at least an inverter.
6. A pulse generator (100) in accordance to claim 1, wherein the signal generator
(14) further comprises at least a monostable circuit, at least an electronic gate, and at least an inverter.
7. A pulse generator (100) in accordance to claim 1, wherein the integrator (15) further comprises at least an electronic gate, and at least an inverter.
8. A pulse generator (100) in accordance to claim 1, wherein the signal generator (14) and the integrator (15) are connected to a delaying means for controlling the signal and providing a predetermined time delay.
9. A method for producing pulse by means of the pulse generator (100) as claimed in claim 1, comprises the steps of:
receiving an input signal;
generating a modified signal;
dividing the modified signal;
triggering a pulse signal of the divided signal at a rising edge; setting a predetermined pulse width for each divided signals;
combining the divided signals for producing an output signal; characterized by the pulse generator (100) instituting time delay of the signals using a delaying means (22), and producing constant output pulse width signals notwithstanding variations in the received input signals.
PCT/MY2013/000240 2012-12-18 2013-12-06 A constant pulse width generator WO2014098558A1 (en)

Applications Claiming Priority (2)

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MYPI2012701209A MY163408A (en) 2012-12-18 2012-12-18 A constant pulse width generator

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3701954A (en) * 1971-07-07 1972-10-31 Us Navy Adjustable pulse train generator
US4245167A (en) * 1978-12-08 1981-01-13 Motorola Inc. Pulse generator for producing fixed width pulses
US6353349B1 (en) * 1998-06-22 2002-03-05 Integrated Silicon Solution Incorporated Pulse delay circuit with stable delay
JP2002190399A (en) * 2000-12-22 2002-07-05 Mega Chips Corp Pulse generator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3701954A (en) * 1971-07-07 1972-10-31 Us Navy Adjustable pulse train generator
US4245167A (en) * 1978-12-08 1981-01-13 Motorola Inc. Pulse generator for producing fixed width pulses
US6353349B1 (en) * 1998-06-22 2002-03-05 Integrated Silicon Solution Incorporated Pulse delay circuit with stable delay
JP2002190399A (en) * 2000-12-22 2002-07-05 Mega Chips Corp Pulse generator

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