WO2015096683A1

WO2015096683A1 - Semiconductor component and manufacturing method therefor

Info

Publication number: WO2015096683A1
Application number: PCT/CN2014/094574
Authority: WO
Inventors: 程凯
Original assignee: 苏州晶湛半导体有限公司
Priority date: 2013-12-25
Filing date: 2014-12-23
Publication date: 2015-07-02
Also published as: CN103632948B; CN103632948A

Abstract

A method for manufacturing a semiconductor component, comprising: providing a substrate (1); forming sequentially on the substrate (1) a semiconductor layer (2), a silicon attachment layer (3), and a photolithographic mask layer (4); etching on some regions on the silicon attachment layer (3) to form oblique sections along the crystal surface of silicon (111), constituting a trapezoidal groove with the crystal surface of non-etched silicon (100), until the semiconductor layer (2) is exposed; and finally, depositing a metal in the groove to form an electrode (5). The semiconductor component manufactured with the method utilizes anisotropic characteristics provided by the silicon attachment layer in the etching process to control and optimize the structure and shape of the electrode, allows for improved electric field distribution of the semiconductor layer, thus increasing the breakdown voltage of the component, and at the same time, also allows for effectively reduced electrode size of the component, thus further improving characteristics of the component such as frequency.

Description

Semiconductor device and method of manufacturing same

The present application claims priority to Chinese Patent Application No. 2013-0726666.0, entitled "Semiconductor Device and Its Manufacturing Method", filed on Dec. 25, 2013, the entire contents of in.

Technical field

The invention belongs to the field of microelectronics, and in particular relates to a method for manufacturing a semiconductor device, and a semiconductor device produced by the method.

Background technique

In the fabrication of semiconductor devices including transistors and diodes, the shape and structure of the triode gate or diode anode tends to play a critical role in many important features of the device. In field effect transistors, the shape and structure of the gate have an important influence on the distribution of charge in the semiconductor layer, and thus have an important influence on the magnitude of the electric field strength and the distribution of the potential. For example, in a gallium nitride high electron mobility transistor (HEMT), when the source-drain voltage is high (eg, over 100V), there is a peak of electric field strength at the edge of the gate near the drain end, which is highly prone to occur at this position. Device breakdown phenomenon, which greatly reduces the breakdown voltage of the device, affects the operating voltage range of the device, and even seriously affects the reliability of the device.

To solve this problem, two methods are usually used: making the gate of the field plate structure and the T-gate. However, both gate shapes require complex processes, and the formation of more gate shapes requires more complex processes, which makes gate shape and structure a major problem limiting device performance and reliability.

On the other hand, in order to improve the performance of the semiconductor device, as the semiconductor manufacturing process progresses, the feature size of the device is gradually reduced. In gallium nitride high electron mobility field effect transistors used in high frequency applications, the size of the gate has an important influence on the frequency characteristics of the device. Increasing the operating frequency of the device often requires the gate to have as small a size as possible to reduce gate parasitics (such as parasitic capacitance and parasitic inductance), thereby reducing the delay caused by the gate, improving the response speed and operation of the device. frequency. At the same time, in order to increase the operating frequency of the device, the gate is required to have a very small size, which can reach a deep sub-micron level. However, such a fine size greatly increases the difficulty of the photolithography process. The conventional photolithography machine cannot meet the process requirements, and an electron beam lithography machine is required to realize a smaller line width.

Therefore, in view of the above technical problems, it is necessary to provide a semiconductor device having an improved structure to overcome the above drawbacks.

Summary of the invention

In view of the above, it is an object of the present invention to provide a method of fabricating a semiconductor device which is controlled and optimized for electrode structure and shape by adding an additional layer of silicon having anisotropy during etching. And further reduce the feature size of the device during lithography.

In the silicon lattice cubic structure shown in Fig. 1(a), the length of the silicon (111) side is the length of the silicon (100) side.

Times, calculate the angle between the crystal orientation of silicon (100) and the crystal orientation of silicon (111)

Similarly, the angle between the silicon (100) crystal plane and the silicon (111) crystal plane is also θ = 55°. FIG. 1(b) is a schematic cross-sectional view showing a trapezoidal groove formed when a silicon semiconductor layer is etched using a potassium hydroxide solution, since the silicon (100) crystal plane is horizontal, and silicon is wet-etched (for wet etching). 111) An oblique section is formed, as shown by the two waists of the trapezoid in Figure 1(b). The angle between the oblique section and the horizontal plane is θ=55°. In Fig. 2(b), a is the upper side of the trapezoidal groove, the opening width of the silicon (100) semiconductor in contact with the potassium hydroxide solution and etching; b is the height of the electrode groove, indicating that the silicon (100) semiconductor layer is The thickness of the etching; c is the lower side of the trapezoidal groove, which is the width of the silicon (100) semiconductor layer which is formed by etching after contact with the active semiconductor layer, and is also the width of the metal electrode in contact with the active semiconductor layer. Combined with the relationship between the silicon (100) plane and the silicon (111) plane in Figure 1(a), it can be calculated.

For example, if the opening width of silicon etching is a=500 nm, when the thickness of silicon is b=100 nm, the width of the metal electrode in contact with the active semiconductor layer can be obtained as c=358 nm, that is, the opening of the opening is etched by this method. The width is reduced from 500 nm to 358 nm; if the thickness b of the silicon becomes 300 nm, the width of the metal electrode at the junction with the active semiconductor layer is c=75 nm, that is, the width of the etching opening is reduced from 500 nm to 75 nm, thus increasing corrosion The process greatly reduces the effective width of the metal electrode. This method not only does not impose strict requirements on the lithography machine, but also increases the effective width of the metal electrode by increasing the thickness of the silicon etching, and even breaks the limit of the lithography machine. It should be noted that this method imposes a certain limitation on the thickness of silicon. In the above example, when the thickness of silicon reaches or exceeds 353 nm, the trapezoidal groove will become a triangular groove, that is, the width of the metal electrode in contact with the active semiconductor layer. Will be reduced to 0.

The above is based on the silicon (100) crystal orientation and the horizontal plane level and the angle between the oblique section and the horizontal plane is θ=55°. In order to ensure the etching to form the above trapezoidal groove, the silicon (100) crystal orientation and the horizontal plane can be formed. - An angle of -35 to 35 degrees.

To achieve the above object, the present invention provides a method of fabricating a semiconductor device comprising the steps of:

1. providing a substrate;

2. forming a semiconductor layer on the substrate;

3. forming an additional silicon layer on the above semiconductor layer;

4. forming a photolithographic mask layer on the above silicon additional layer;

5. etching a partial region on the silicon additional layer, forming an oblique cross section along the silicon (111) crystal plane, forming a trapezoidal recess with the unetched silicon (100) crystal plane, etching until the semiconductor layer is exposed ;

6. Depositing a metal on the recess to form an electrode.

Preferably, in step 3, the (100) crystal plane of the silicon additional layer forms an angle of -35 to 35 degrees with the horizontal plane of the semiconductor layer.

Preferably, in step 3, the additional silicon layer is formed by one or more of deposition, epitaxial growth, and wafer bonding.

Preferably, before step 3, a dielectric layer is interposed between the silicon additional layer and the semiconductor layer, including silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino and dioxide. One or several of silicon.

Preferably, in step 4, the lithographic mask layer is in photoresist, silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino, and silicon dioxide. One or several.

Preferably, in step 6, the electrode is formed by depositing metal in the trapezoidal groove, and then the additional layer of silicon is removed; or the additional layer of silicon is first oxidized or nitrided to completely convert the additional layer of silicon into silicon dioxide or silicon nitride. Or a silicon oxynitride insulating medium, and then an electrode is formed in the trapezoidal groove.

Further, after step 3 forms an additional layer of silicon, a passivation dielectric layer is formed on the additional layer of silicon, and a photolithographic mask layer is formed on the passivation dielectric layer, and is passivated after etching the additional layer to form a trapezoidal recess. The dielectric layer is etched.

Further, in step 6, before depositing the metal to form the electrode, the dielectric layer is deposited to form an insulating dielectric layer between the metal electrode and the semiconductor layer.

A semiconductor device manufactured by the above method, comprising:

Substrate

a semiconductor layer on the substrate;

An etch-time anisotropic silicon additional layer on the semiconductor layer;

And a trapezoidal recess formed by etching on the additional layer of silicon and an electrode deposited in the trapezoidal recess.

Preferably, a passivation dielectric layer is further disposed between the semiconductor layer and the silicon additional layer.

Preferably, the passivation dielectric layer is one or more of silicon nitride, silicon germanium nitrogen, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino, and silicon dioxide.

Preferably, the substrate is silicon, silicon carbide, germanium, silicon or sapphire on sapphire.

Preferably, the semiconductor layer is one or more of silicon, germanium, germanium silicon, group III arsenide, group III phosphide, and group III nitride.

Preferably, the electrode shape is T-shaped or Γ-shaped.

Preferably, the electrode has a field plate structure.

It can be seen from the above technical solution that the semiconductor device of the present invention utilizes the anisotropic characteristics of the etching process of the silicon additional layer to control and optimize the electrode structure and shape, thereby improving the electric field distribution of the semiconductor layer, thereby improving the device. Breakdown voltage; at the same time, it can effectively reduce the electrode size of the device, and further improve the frequency characteristics of the device.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. Obviously, the related description in the following description The drawings are only some of the embodiments of the present invention, and other drawings may be obtained from those skilled in the art without departing from the drawings.

1(a) is a schematic view showing the structure of a silicon (100) crystal orientation and a silicon (111) crystal orientation, and FIG. 1(b) is a schematic cross-sectional structural view of a trapezoidal recess;

2(a) and 2(b) to 2(h) are schematic cross-sectional structural views of a semiconductor device having a silicon (100) thin film semiconductor mask layer according to Embodiment 1 of the present invention;

3(a), 3(b), 3(c), and 3(d) are cross-sectional structures of a fabrication process of a semiconductor device having a silicon (100) thin film semiconductor layer and a passivation dielectric layer according to Embodiment 2 of the present invention; Schematic diagram of change

4 is a cross-sectional structural view showing a semiconductor device including a passivation dielectric layer and an oxidized additional layer according to Embodiment 3 of the present invention;

5 is a schematic cross-sectional view showing a semiconductor device including a gate dielectric layer between an electrode metal and an active semiconductor layer according to Embodiment 4 of the present invention;

6 is a schematic cross-sectional view showing a metal oxide field effect transistor (MOSFET) including a gate oxide layer between a semiconductor layer and an additional layer in Embodiment 5 of the present invention.

detailed description

The invention discloses a method for manufacturing a semiconductor device, comprising the following steps:

1. providing a substrate;

2. forming a semiconductor layer on the substrate;

3. forming an additional silicon layer on the above semiconductor layer;

6. Depositing a metal on the recess to form an electrode.

A semiconductor device manufactured by the above method, comprising:

Substrate

a semiconductor layer on the substrate;

An etch-time anisotropic silicon additional layer on the semiconductor layer;

Preferably, the electrode shape is T-shaped or Γ-shaped.

Preferably, the electrode has a field plate structure.

The technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Example 1

As shown in FIG. 2(a), the semiconductor device includes: a substrate 1; a gallium nitride semiconductor layer 2 on the substrate 1, a silicon semiconductor additional layer 3 on the semiconductor layer 2, and an electrode region in the additional layer 3 a groove formed by etching; an electrode 4 formed at the groove. The substrate 1 in this embodiment may be silicon, silicon carbide, germanium, silicon or sapphire on sapphire. The semiconductor device in this embodiment may be Schottky The diode may also be a metal insulator field effect transistor (MISFET), including a metal oxide field effect transistor (MOSFET), or a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), or a heterojunction. Field effect transistor (HFET). The semiconductor layer in this embodiment may be any one or a combination of silicon, germanium, gallium arsenide, gallium nitride, aluminum nitride, aluminum gallium nitride, and aluminum gallium indium nitride.

As shown in FIGS. 2(b), 2(c), 2(d), 2(e), 2(f), 2(g), and 2(h), the method of manufacturing the semiconductor device in the present embodiment is: (1) a substrate 1 is provided as shown in FIG. 2(b); (2) a semiconductor layer 2 is formed on the substrate 1 as shown in FIG. 2(c), wherein the semiconductor layer 2 may include a channel layer and The heterojunction formed by the contact of the barrier layer may also include a quantum well structure formed of a homogeneous semiconductor of different polarity (such as any one of silicon or gallium nitride); (3) as shown in FIG. 2(d), Forming an additional layer 3 on the semiconductor layer 2, wherein the additional layer may comprise a silicon (100) thin film semiconductor; (4) as shown in Figure 2 (e), forming a photolithographic mask layer 4 on the additional layer 3; (5) as shown in FIG. 2(f), the portion to be etched under the lithographic mask layer is exposed by photolithography; (6) as shown in FIG. 2(g), including wet etching by etching, The groove is etched in the additional layer electrode region; since the silicon has the characteristics of anisotropy during wet etching, the etching rate is slow in the (111) direction, and a trapezoidal groove of silicon (111) plane is formed; (7) As shown in FIG. 2(h), the photolithographic mask layer 4 is removed, and a metal is formed by depositing a metal in the trapezoidal recess. Trapezoidal electrode 5. It is also possible to oxidize the silicon thin film semiconductor layer in the additional layer to silicon dioxide, and then form the electrode 5 having a trapezoidal structure in the formed trapezoidal groove.

In this embodiment, the anisotropic property of the silicon additional layer when etching with a potassium hydroxide solution, that is, the rate of etching or etching in the (100) direction is large, and the etching in the (111) direction or etching is performed. The rate is small, and a slope is formed on the silicon (111) crystal plane during the etching process. The cross-sectional shape of the groove will present an inverted trapezoid that is about an angle of about 55 degrees down. As the thickness of the silicon semiconductor layer is increased, the height of the inverted trapezoidal section of the groove profile is gradually increased during the etching process, so that the downward inclination angle of the inverted trapezoidal waist is maintained at about 55 degrees. In this case, the side length of the underlying trapezoid, that is, the side of the gallium nitride semiconductor layer, will gradually decrease, resulting in a gradual decrease in the effective length of the electrode metal in contact with the gallium nitride semiconductor layer. After the additional layer forms a trapezoidal recess, the electrode metal is then deposited at the trapezoidal recess to form a trapezoidal electrode structure. This method enables us to change the size of the electrode metal in contact with the gallium nitride semiconductor layer by controlling the thickness of the additional layer, ie, the silicon (100) thin film semiconductor layer, which can effectively reduce the equivalent size of the electrode and thereby improve The shape and structure of the electrode. This method makes it possible to produce extremely fine electrodes without using an electron beam lithography machine, which not only greatly reduces the dependence on the electron beam lithography machine, but also minimizes the gate size to the deepest. Submicron or even nanoscale.

Example 2

The semiconductor device includes a substrate 1, a semiconductor layer 2, a passivation layer 3, an additional layer 4, and an electrode 5. This embodiment differs from Embodiment 1 in that a passivation dielectric layer 3 is added between the semiconductor layer 2 and the additional layer 4. The passivation dielectric layer 3 may include a combination of one or more of silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino, and silicon dioxide.

As shown in FIG. 3(a), FIG. 3(b), FIG. 3(c), and FIG. 3(d), after the inverted trapezoidal electrode recess is formed by etching the additional layer 4, that is, the silicon (100) thin film semiconductor layer, The size of the electrode recess can be greatly reduced. Then, by etching the silicon nitride passivation layer 3 under the inverted trapezoidal recess, the recess of the silicon nitride layer 3 formed by etching and the additional layer 4, that is, the electrode recess on the silicon (100) thin film semiconductor The lower side of the inverted trapezoid has the same size, and then the metal is deposited in the T-shaped groove formed by the superposition of the additional layer 4 and the silicon nitride layer 3 to form the T-type electrode 5. Finally, the additional layer 4 is removed, A T-shaped electrode structure 5 suspended on both sides of the upper end is formed. An advantage of such an electrode structure is that since the groove formed by the additional layer 4 has a trapezoidal structure, the additional layer under the electrode is relatively easy to remove and is not easily left. Compared with the conventional T-shaped electrode structure which is not suspended on both sides, the T-shaped electrode structure which is suspended on both sides of the upper end formed by the above method has the lowest dielectric constant because the two sides of the medium are air, so the structure has relatively good Low parasitic capacitance is beneficial to improve important characteristics such as the frequency characteristics of semiconductor devices, especially field effect transistors used in the RF field.

Example 3

The semiconductor device includes a substrate 1, a semiconductor layer 2, a passivation layer 3, an additional layer 4, and an electrode 5. Compared with Embodiment 2, the present embodiment is different in that, as shown in FIG. 4, a passivation dielectric layer 3 is added between the active semiconductor layer 2 and the silicon additional layer 4, and an improved structure is formed in the electrode recess. After the electrode metal, the silicon additional layer 4 is oxidized to form the silicon dioxide layer 4 without removing the silicon additional layer 4. This allows a layer of silicon dioxide 4 to be added over the passivation layer 3 to function as a dielectric layer and a protective layer. The passivation dielectric layer 3 may include a combination of one or more of silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino, and silicon dioxide. Other structures and fabrication methods are the same as in Embodiment 2.

Example 4

The semiconductor device includes a substrate 1, a semiconductor layer 2, a passivation layer 3, an additional layer 4, a dielectric layer 5, and an electrode 6. Compared with Embodiment 3, the present embodiment is different in that, as shown in FIG. 5, before depositing the electrode metal, the dielectric layer 5 is deposited to form an insulating dielectric layer as the metal electrode 6 and the active semiconductor layer 2, forming Insulated gate semiconductor device. The advantage of the insulated gate field effect transistor fabricated by this method is that the T-type gate structure fabricated by the method has a small equivalent. The size and the charge distribution of the gate electrode are improved, and the frequency characteristics and withstand voltage characteristics of the semiconductor device are improved. Other structures and manufacturing methods are the same as in the third embodiment.

Example 5

The semiconductor device includes a substrate 1, a semiconductor layer 2, an additional layer 4, and

electrodes

31, 32, and 33. Compared with Embodiment 1, the present embodiment is different in that the semiconductor device is a MOSFET, a gate oxide layer is included between the semiconductor layer and the additional layer, the additional layer is silicon, and the gate oxide layer is Silica is formed by oxidation of an additional layer of silicon. As shown in FIG. 6, after an additional layer is formed on the semiconductor layer 2, a trapezoidal electrode recess is formed by etching anisotropy of the additional layer of silicon, and then the additional layer of silicon is oxidized to a silicon dioxide layer as a gate oxide of the MOSFET. Floor. The improved gate structure formed by the above method can reduce the effective size of the gate and improve the frequency characteristics of the device.

In summary, the semiconductor device of the present invention utilizes the anisotropic characteristics of the etching process of the additional layer to control and optimize the electrode structure and shape, and can improve the electric field distribution of the semiconductor layer, thereby improving the breakdown voltage of the device; At the same time, the electrode size of the device can be effectively reduced, and the frequency characteristics of the device can be further improved.

It is apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the invention is defined by the appended claims instead All changes in the meaning and scope of equivalent elements are included in the present invention. Any reference signs in the claims should not be construed as limiting the claim.

In addition, it should be understood that although the description is described in terms of embodiments, not every embodiment includes only one independent technical solution. The description of the specification is merely for the sake of clarity, and those skilled in the art should regard the specification as a whole. The technical solutions in the respective embodiments may also be combined as appropriate to form other embodiments that can be understood by those skilled in the art.

Claims

A method of fabricating a semiconductor device, comprising the steps of:

(1) providing a substrate;

(2) forming a semiconductor layer on the above substrate;

(3) forming an additional silicon layer on the above semiconductor layer;

(4) forming a photolithographic mask layer on the above silicon additional layer;

(5) etching a partial region on the silicon additional layer, forming an oblique cross section along the silicon (111) crystal plane, forming a trapezoidal recess with the unetched silicon (100) crystal plane, etching until the semiconductor is exposed Floor;

(6) Depositing a metal in the above groove to form an electrode.
The manufacturing method according to claim 1, wherein in the step (3), the (100) crystal plane of the silicon additional layer forms an angle of -35 to 35 degrees with the horizontal plane of the semiconductor layer.
The manufacturing method according to claim 1, wherein in the step (3), the additional silicon layer is formed by one or more of deposition, epitaxial growth, and wafer bonding.
The manufacturing method according to claim 1, wherein before the step (3), a dielectric layer is interposed between the silicon additional layer and the semiconductor layer, including silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicon aluminum One or more of oxygen, aluminum magnesium oxynitride, silicoalumino and silica.
The manufacturing method according to claim 1, wherein after the step (3) forms an additional silicon layer, a passivation dielectric layer is formed on the silicon additional layer, and a photolithographic mask layer is formed on the passivation dielectric layer, and The passivation dielectric layer is etched after the silicon additional layer is etched to form a trapezoidal recess.
The manufacturing method according to claim 1, wherein in the step (4), the photolithographic mask layer is photoresist, silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicon aluminum oxide, aluminum One or more of magnesium oxynitride, silicoalumino and silica.
The manufacturing method according to claim 1, wherein in the step (6), the electrode is formed by depositing a metal in the trapezoidal groove, and then the additional layer of silicon is removed; or the additional layer of silicon is first oxidized and then trapezoidally concave. An electrode is formed in the groove.
The manufacturing method according to claim 1, wherein in the step (6), before depositing the metal to form the electrode, the dielectric layer is deposited to form an insulating dielectric layer between the metal electrode and the semiconductor layer.
A semiconductor device manufactured by the manufacturing method of claim 1, comprising:

Substrate

a semiconductor layer on the substrate;

An etch-time anisotropic silicon additional layer on the semiconductor layer;

And a trapezoidal recess formed by etching on the additional layer of silicon and an electrode deposited in the trapezoidal recess.
The semiconductor device according to claim 9, wherein a passivation dielectric layer is further provided on said silicon additional layer.
The semiconductor device according to claim 10, wherein said passivation dielectric layer is silicon nitride, silicon germanium nitride, silicon aluminum gallium nitride, silicoalumino, aluminum magnesium oxynitride, silicoalumino and silicon dioxide. One or several of them.
The semiconductor device according to claim 9, wherein said substrate is silicon, silicon carbide, germanium, silicon or sapphire on sapphire.
The semiconductor device according to claim 9, wherein said semiconductor layer is one or more of silicon, germanium, germanium silicon, group III arsenide, group III phosphide, and group III nitride.
The semiconductor device according to claim 9, wherein said electrode shape is a T-shape or a Γ-type.
The semiconductor device according to claim 9, wherein said electrode has a field plate structure.