Memory array having selected word lines driven to an internally-generated ...

1. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

a voltage generator circuit for generating, on an output node thereof, a substantially fixed boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

a row decoder circuit coupled to receive the boosted voltage, for decoding a selected word line and driving the selected word line to the boosted voltage during a memory operation.

2. An integrated circuit as in claim 1 wherein the integrated circuit further comprises:

an array select control circuit coupled to receive the boosted voltage, for decoding at least one selected array select signal and driving the at least one selected array select signal to the boosted voltage during a memory operation.

3. An integrated circuit as in claim 2 wherein:

the array select control circuit is arranged to drive, during a memory operation, the at least one selected array select signal to the boosted voltage from an initial voltage equal to the power supply voltage.

4. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

a voltage generator circuit for generating, on an output node thereof, a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

a row decoder circuit coupled to receive the boosted voltage, for decoding a selected word line and driving the selected word line to the boosted voltage during a memory operation;

wherein the voltage generator circuit comprises:

a reference voltage circuit for internally generating a reference voltage;

a controller circuit coupled to receive the boosted voltage and the internally generated reference voltage, for at least determining whether the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value; and

at least one pump circuit responsive to the controller circuit for periodically coupling charge onto the output node of the voltage generator circuit when the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value, thereby tending to increase the magnitude of the boosted voltage relative to the ground potential.

5. An integrated circuit as in claim 4 wherein:

the reference voltage circuit comprises a bandgap reference voltage circuit; and

the internally generated reference voltage is substantially independent of the power supply voltage, substantially independent of variations in semiconductor process parameters, and substantially independent of variations in temperature.

6. An integrated circuit as in claim 4 wherein:

the controller circuit is also coupled to receive the power supply voltage, for controlling the amount of charge coupled periodically onto the output node of the voltage generator circuit as a function of both the boosted voltage and the power supply voltage.

7. An integrated circuit as in claim 4 wherein the voltage generator circuit further comprises:

a plurality of pump circuits, each independently enabled by the controller circuit for periodically coupling a corresponding amount of electronic charge per pump cycle onto the output node of the voltage generator circuit.

8. An integrated circuit as in claim 7 wherein the controller circuit comprises:

a first regulator circuit coupled to receive the boosted voltage and the internally generated reference voltage, for outputting at least one control signal when the magnitude of the boosted voltage is less than its desired regulated value; and

a pump control circuit, responsive to the at least one control signal from the first regulator circuit, for determining if one or more of the plurality of pump circuits should be enabled as a function of the boosted voltage relative to its desired regulated value, and for controlling each of the plurality of pump circuits in accordance therewith.

9. An integrated circuit as in claim 8 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing the internally generated reference voltage to a respective one of a plurality of voltages proportional to the boosted voltage.

10. An integrated circuit as in claim 8 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing a voltage proportional to the boosted voltage to a respective one of a plurality of voltages proportional to the internally generated reference voltage.

11. An integrated circuit as in claim 8 wherein the controller circuit further comprises:

a second regulator circuit coupled to receive the power supply voltage and the internally generated reference voltage, for outputting at least one control signal indicative of the magnitude of the power supply voltage; and

wherein the pump control circuit is also responsive to the at least one control signal from the second regulator circuit, for determining if one or more of the plurality of pump circuits should be enabled as a function of both the power supply voltage and the boosted voltage relative to its desired regulated value, and for controlling each of the plurality of pump circuits in accordance therewith.

12. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

a voltage generator circuit for generating, on an output node thereof, a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

a row decoder circuit coupled to receive the boosted voltage, for decoding a selected word line and driving the selected word line to the boosted voltage during a memory operation;

wherein the voltage generator circuit further comprises:

a test input coupled to receive a test mode signal, to alter by a particular amount the voltage to which the boosted voltage is regulated when the test mode signal is active.

13. An integrated circuit as in claim 11 wherein the controller circuit is arranged such that:

whenever the boosted voltage is less in magnitude than a lower limit, all the pump circuits are enabled;

whenever the boosted voltage is greater in magnitude than an upper limit, none of the pump circuits are enabled; and

whenever the magnitude of the boosted voltage falls between the lower limit and the upper limit, a variable number of the pump circuits are enabled as a function of both the power supply voltage and the boosted voltage.

14. An integrated circuit as in claim 13 wherein the controller circuit further comprises:

a test input coupled to receive a test mode signal, to lower in magnitude by a particular amount the lower limit voltage and the upper limit voltage when the test mode signal is active.

15. An integrated circuit as in claim 11 wherein:

each of the plurality of pump circuits are individually sized so that, as the power supply voltage varies over its anticipated operating range, and as the number and pumping capacity of pump circuits that are enabled varies accordingly, the peak magnitude of electronic charge pumped per cycle, just before each change in the selection of pump circuits so enabled, is substantially uniform over the anticipated operating range of the power supply voltage.

16. An integrated circuit as in claim 1 wherein:

the row decoder circuit is arranged so that deselected row decoders provide significant capacitive load on the boosted output node of the voltage generator circuit when compared to the capacitance of a selected word line within the memory array that must be charged to the boosted voltage during each memory cycle, such capacitive load providing a significant reservoir of electronic charge on the boosted output node without requiring separate devices or structures.

17. An integrated circuit as in claim 1 wherein the memory array comprises a dynamic memory array.

18. An integrated circuit as in claim 1 wherein the memory array comprises a read-only memory array.

19. An integrated circuit as in claim 1 wherein:

the power supply voltage is a positive voltage relative to the ground potential; and

the boosted voltage is more positive than the power supply voltage.

20. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

a voltage generator circuit for generating, on an output node thereof, a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

a row decoder circuit coupled to receive the boosted voltage, for decoding a selected word line and driving the selected word line to the boosted voltage during a memory operation;

wherein the voltage generator circuit comprises:

a controller circuit coupled to receive the boosted voltage and the power supply voltage;

a plurality of pump circuits responsive to the controller circuit, each having a respective size pump capacitance, for periodically coupling electronic charge onto the output node of the voltage generator circuit, thereby tending to increase the magnitude of the boosted voltage;

wherein each of the plurality of pump circuits may be independently enabled by the controller circuit to couple a corresponding amount of electronic charge per pump cycle onto the output node of the voltage generator circuit;

wherein, for a given value of the power supply voltage, the controller circuit is arranged to enable one or more pump circuits having, in aggregate, incrementally more total pump capacitance as the magnitude of the boosted voltage tends further below its desired regulated value, and to disable all pump circuits if the magnitude of the boosted voltage exceeds its desired regulated value; and

wherein, for a given value of the boosted voltage, the controller circuit is arranged to enable one or more pump circuits having, in aggregate, incrementally more total pump capacitance as the magnitude of the power supply voltage tends correspondingly further below its nominal value, and to enable one or more pump circuits having, in aggregate, incrementally less total pump capacitance as the magnitude of the power supply voltage tends correspondingly further above its nominal value, thereby tending to maintain a more uniform value of total pumped charge per cycle over an operating range of the power supply voltage.

21. An integrated circuit as in claim 20 wherein:

the memory array comprises a dynamic memory array;

the power supply voltage is a positive voltage relative to the ground potential; and

the boosted voltage is more positive than the power supply voltage.

22. An integrated circuit as in claim 21 wherein the integrated circuit further comprises:

an array select control circuit coupled to receive the boosted voltage, for decoding at least one selected array select signal and driving the at least one selected array select signal from an initial voltage equal to the power supply voltage up to the boosted voltage during a memory operation.

23. An integrated circuit as in claim 20 wherein:

each of the plurality of pump circuits are individually sized so that, as the power supply voltage varies over its anticipated operating range, and as the number and pumping capacity of pump circuits that are enabled varies accordingly, the peak magnitude of electronic charge pumped per cycle, just before each change in the selection of pump circuits so enabled, is substantially uniform over the anticipated operating range of the power supply voltage.

24. An integrated circuit as in claim 20 wherein the controller circuit comprises:

a reference voltage circuit for internally generating a reference voltage;

a first regulator circuit coupled to receive the boosted voltage and the internally generated reference voltage, for generating a first voltage related to the boosted voltage and a second voltage related to the internally generated reference voltage, for comparing the first voltage to the second voltage to infer a determination of the boosted voltage, and for outputting at least one control signal in accordance therewith;

a second regulator circuit coupled to receive the power supply voltage and the internally generated reference voltage, for generating a third voltage related to the power supply voltage, for comparing the third voltage to a voltage related to the internally generated reference voltage to infer a determination of the power supply voltage, and for outputting at least one control signal in accordance therewith; and

a pump control circuit, responsive to the at least one control signal from the first regulator circuit and responsive to the at least one control signal from the second regulator circuit, for determining if one or more of the plurality of pump circuits should be enabled, and for controlling each of the plurality of pump circuits in accordance therewith.

25. An integrated circuit as in claim 24 wherein:

the first voltage comprises a linear fraction of the boosted voltage; and

the second voltage is substantially equal to the internally generated reference voltage.

26. An integrated circuit as in claim 24 wherein:

the third voltage comprises a linear fraction of the power supply voltage; and

the voltage to which the third voltage is compared is substantially equal to the internally generated reference voltage.

27. An integrated circuit as in claim 24 wherein:

the first voltage comprises a linear fraction of the boosted voltage;

the second voltage is substantially equal to the internally generated reference voltage;

the third voltage comprises a linear fraction of the power supply voltage; and

the voltage to which the third voltage is compared is substantially equal to the internally generated reference voltage.

28. An integrated circuit as in claim 26 wherein:

the reference voltage circuit comprises a bandgap reference voltage circuit; and

the internally generated reference voltage is substantially independent of the power supply voltage, substantially independent of variations in semiconductor process parameters, and substantially independent of variations in temperature.

29. An integrated circuit as in claim 24 wherein the controller circuit further comprises:

a test input coupled to receive a test mode signal, to lower by a particular amount the voltage to which the boosted voltage is regulated when the test mode signal is active.

30. An integrated circuit as in claim 29 wherein:

the particular amount by which the boosted voltage is altered, when the test mode signal is active, is approximately 200 mV.

31. In an integrated circuit having a memory array, a method of operating the integrated circuit comprising:

receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

generating a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and then

driving a selected word line to the boosted voltage during a memory operation.

32. A method as in claim 31 further comprising:

decoding at least one selected array select signal; and

driving the at least one selected array select signal to the boosted voltage during a memory operation.

33. A method as in claim 32 wherein:

the at least one selected array select signal is driven from an initial voltage equal to the power supply voltage to the boosted voltage during a memory operation.

34. A method as in claim 31 wherein the generating step comprises:

determining whether the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value; and

periodically coupling charge onto the boosted output node when the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value, thereby tending to increase the magnitude of the boosted voltage relative to the ground potential.

35. A method as in claim 34 further comprising:

controlling the amount of charge coupled periodically onto the output node of the voltage generator circuit as a function of both the boosted voltage and the power supply voltage.

36. In an integrated circuit having a memory array, a method of operating the integrated circuit comprising:

receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

generating a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

driving a selected word line to the boosted voltage during a memory operation;

wherein the generating step comprises:

determining whether the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value; and

periodically coupling charge onto the boosted output node when the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value, thereby tending to increase the magnitude of the boosted voltage relative to the ground potential; and

wherein the amount of charge coupled onto the boosted output node is controlled by varying which one or ones of a plurality of pump circuits are enabled.

37. A method as in claim 36 further comprising:

generating a first voltage related to the boosted voltage and a second voltage related to the internally generated reference voltage;

comparing the first voltage to the second voltage;

outputting at least one control signal when the magnitude of the boosted voltage is less than desired;

determining if one or more of the plurality of pump circuits should be enabled as a function of the boosted voltage relative to its desired regulated value; and

controlling each of the plurality of pump circuits in accordance therewith.

38. A method as in claim 37 further comprising:

generating a third voltage related to the power supply voltage;

comparing the third voltage to a voltage related to the internally generated reference voltage;

outputting at least one control signal indicative of the magnitude of the power supply voltage;

determining if one or more of the plurality of pump circuits should be enabled as a function of both the power supply voltage and the boosted voltage relative to its desired regulated value; and

controlling each of the plurality of pump circuits in accordance therewith.

39. In an integrated circuit having a memory array, a method of operating the integrated circuit comprising:

receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

generating a boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage;

driving a selected word line to the boosted voltage during a memory operation;

receiving a test mode signal; and

altering by a particular amount the voltage to which the boosted voltage is regulated when the test mode signal is active.

40. A method as in claim 38 further comprising:

whenever the boosted voltage is less in magnitude than a lower limit, enabling all the pump circuits;

whenever the boosted voltage is greater in magnitude than an upper limit, enabling none of the pump circuits; and

whenever the magnitude of the boosted voltage falls between the lower limit and the upper limit, enabling a variable number of the pump circuits as a function of both the power supply voltage and the boosted voltage.

41. A method as in claim 38 wherein:

each of the plurality of pump circuits are individually sized so that, as the power supply voltage varies over its anticipated operating range, and as the number and pumping capacity of pump circuits that are enabled varies accordingly, the peak magnitude of electronic charge pumped per cycle, just before each change in the selection of pump circuits so enabled, is substantially uniform over the anticipated operating range of the power supply voltage.

42. A method as in claim 31 wherein:

row decoder circuitry is arranged so that deselected row decoders provide significant capacitive load on the boosted voltage node when compared to the capacitance of a selected word line within the memory array that must be charged to the boosted voltage during each memory cycle, such capacitive load providing a significant reservoir of electronic charge on the boosted voltage node without requiring separate devices or structures.

43. A method as in claim 31 wherein the memory array comprises a dynamic memory array.

44. A method as in claim 31 wherein the memory array comprises a read-only memory array.

45. A method as in claim 31 wherein:

the power supply voltage is a positive voltage relative to the ground potential; and

the boosted voltage is more positive than the power supply voltage.

46. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a power supply voltage operably coupled to the integrated circuit, by which voltage most circuits associated with the memory array are generally powered;

means for generating a substantially fixed boosted voltage having a regulated magnitude, relative to the ground potential, that is substantially independent of the power supply voltage, over at least an expected range of possible operating values for the power supply voltage; and

means for driving a selected word line to the boosted voltage during a memory operation.

47. An integrated circuit as in claim 46 further comprising:

means for decoding at least one selected array select signal; and

means for driving the at least one selected array select signal to the boosted voltage during a memory operation.

48. An integrated circuit as in claim 46 wherein the boosted voltage generation means comprises:

means for determining whether the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value; and

means for periodically coupling charge onto the output node of the voltage generator circuit when the magnitude of the boosted voltage, relative to the ground potential, is less than its desired regulated value, thereby tending to increase the magnitude of the boosted voltage relative to the ground potential.

49. An integrated circuit in claim 47 wherein the boosted voltage generation means further comprises:

means for controlling the amount of charge coupled periodically onto the output node of the voltage generator circuit as a function of both the boosted voltage and the power supply voltage.

50. An integrated circuit as in claim 48 wherein the means for controlling the amount of charge coupled periodically onto the output node of the voltage generator circuit comprises:

means for enabling one or more of a plurality of pump circuits.

51. An integrated circuit comprising:

a memory array including a plurality of memory cells, each memory cell coupled to an associated one of a plurality of word lines within the memory array;

a power supply terminal for receiving, relative to a ground potential, a VDD power supply voltage operably coupled to the integrated circuit;

a voltage generator circuit for generating, on an output node thereof, a boosted VPP voltage that is nominally greater in magnitude than the VDD power supply voltage, over at least an expected range of possible operating values for the VDD power supply voltage; and

a row decoder circuit coupled to receive the VPP voltage, for decoding a selected word line and driving the selected word line to the VPP voltage;

wherein the voltage generator circuit includes

a controller circuit;

a plurality of pump circuits responsive to the controller circuit for periodically coupling electronic charge onto the VPP output node of the voltage generator circuit, thereby tending to increase the magnitude of the VPP voltage;

wherein each of the plurality of pump circuits may be independently enabled by the controller circuit to couple a corresponding amount of electronic charge per pump cycle onto the VPP output node of the voltage generator circuit;

wherein, for a given value of the VPP voltage, the controller circuit is arranged to enable one or more pump circuits having, in aggregate, incrementally more total pump capacitance as the magnitude of the VDD voltage tends correspondingly further below its nominal value, and to enable one or more pump circuits having, in aggregate, incrementally less total pump capacitance as the magnitude of the VDD voltage tends correspondingly further above its nominal value, thereby tending to maintain a more uniform value of total pumped charge per cycle over an operating range of the VDD voltage; and

wherein each of the plurality of pump circuits are individually sized so that, as the VDD voltage varies over its anticipated operating range, and as the number and pumping capacity of pump circuits that are enabled varies accordingly, the peak magnitude of electronic charge pumped per cycle, just before each change in the selection of pump circuits so enabled, is substantially uniform over the anticipated operating range of the VDD voltage.

52. An integrated circuit as in claim 51 wherein:

the controller circuit is further arranged to disable all pump circuits if the magnitude of the VPP voltage exceeds a particular voltage.

53. An integrated circuit as in claim 51 wherein the controller circuit comprises:

a first regulator circuit coupled to receive the VDD voltage and an internally generated reference voltage, for generating a first voltage related to the VDD voltage and a second voltage related to the internally generated reference voltage, for comparing the first voltage to the second voltage and for outputting at least one control signal indicative of the magnitude of the VDD voltage; and

a pump control circuit, responsive to the at least one control signal from the first regulator circuit, for determining if one or more of the plurality of pump circuits should be enabled as a function of the VDD voltage, and for controlling each of the plurality of pump circuits in accordance therewith.

54. An integrated circuit as in claim 53 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing a voltage proportional to the internally generated reference voltage to a respective one of a plurality of voltages proportional to the VDD voltage.

55. An integrated circuit as in claim 53 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing a voltage proportional to the VDD voltage to a respective one of a plurality of voltages proportional to the internally generated reference voltage.

56. In an integrated circuit, a voltage generator circuit for generating, on an output node thereof, a boosted VPP voltage that is nominally greater in magnitude than a VDD power supply voltage operably coupled to the integrated circuit, over at least an expected range of possible operating values for the VDD power supply voltage, said voltage generator circuit comprising:

a controller circuit;

a plurality of pump circuits responsive to the controller circuit for periodically coupling electronic charge onto the VPP output node of the voltage generator circuit, thereby tending to increase the magnitude of the VPP voltage;

wherein each of the plurality of pump circuits may be independently enabled by the controller circuit to couple a corresponding-amount of electronic charge per pump cycle onto the VPP output node of the voltage generator circuit;

wherein, for a given value of the VPP voltage, the controller circuit is arranged to enable one or more pump circuits having, in aggregate, incrementally more total pump capacitance as the magnitude of the VDD voltage tends correspondingly further below its nominal value, and to enable one or more pump circuits having, in aggregate, incrementally less total pump capacitance as the magnitude of the VDD voltage tends correspondingly further above its nominal value, thereby tending to maintain a more uniform value of total pumped charge per cycle over an operating range of the VDD voltage; and

wherein each of the plurality of pump circuits are individually sized so that, as the VDD voltage varies over its anticipated operating range, and as the number and pumping capacity of pump circuits that are enabled varies accordingly, the peak magnitude of electronic charge pumped per cycle, just before each change in the selection of pump circuits so enabled, is substantially uniform over the anticipated operating range of the VDD voltage.

57. A circuit as in claim 56 wherein the controller circuit comprises:

a first regulator circuit coupled to receive the VDD voltage and an internally generated reference voltage, for generating a first voltage related to the VDD voltage and a second voltage related to the internally generated reference voltage, for comparing the first voltage to the second voltage and for outputting at least one control signal indicative of the magnitude of the VDD voltage; and

a pump control circuit, responsive to the at least one control signal from the first regulator circuit, for determining if one or more of the plurality of pump circuits should be enabled as a function of the VDD voltage, and for controlling each of the plurality of pump circuits in accordance therewith.

58. A circuit as in claim 57 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing a voltage proportional to the internally generated reference voltage to a respective one of a plurality of voltages proportional to the VDD voltage.

59. A circuit as in claim 57 wherein the first regulator circuit comprises:

a plurality of sensing circuits, each for comparing a voltage proportional to the VDD voltage to a respective one of a plurality of voltages proportional to the internally generated reference voltage.

60. An integrated circuit as in claim 1 wherein:

the power supply voltage is a positive voltage relative to the ground potential; and

the boosted voltage is lower in magnitude, for certain combinations of semiconductor process parameters, power supply voltage, and temperature, than the power supply voltage.

61. A method as in claim 31 wherein:

the power supply voltage is a positive voltage relative to the ground potential; and

the boosted voltage is lower in magnitude, for certain combinations of semiconductor process parameters, power supply voltage, and temperature, than the power supply voltage.