1. An integrated circuit chip package comprising:
- a dielectric layer;
- a plated throughhole in the dielectric layer; and
- a micro-via coupled with the plated throughhole, wherein the micro-via comprises a plurality of substantially horizontal path layers including a single point of contact between substantially horizontal path layers, wherein the substantially horizontal path layers each contain only a portion of a geometric shape and that only in combination form a closed path around an axis.
2. The integrated circuit chip package of claim 1, wherein the axis is substantially vertical.
3. The integrated circuit chip package of claim 2, wherein the path is substantially rectangular in shape.
4. The integrated circuit chip package of claim 2, wherein the path is substantially circular in shape.
5. The integrated circuit chip package of claim 2, wherein the path comprises at least one loop around the axis.
6. The integrated circuit chip package of claim 2, wherein the path comprises one or more turns in a same layer.
7. The integrated circuit chip package of claim 1, wherein the path comprises a rise at an angle from vertical.
8. An apparatus comprising:
- an integrated circuit die; and
- a substrate, including a dielectric layer, a plurality of plated throughholes in the dielectric layer, and micro-vias coupled with the plated throughholes, wherein the micro-vias comprise a plurality of substantially horizontal path layers including a single point of contact between substantially horizontal path layers, wherein the substantially horizontal path layers each contain only a portion of a geometric shape and that only in combination form a closed path around an axis substantially parallel with the coupled plated throughholes.
9. The apparatus of claim 8, wherein the path is substantially triangular in shape.
10. The apparatus of claim 8, wherein the path is polygonal in shape.
11. The apparatus of claim 8, wherein the path comprises one or more turns in a same layer.
12. An electronic appliance comprising:
- a network controller;
- a system memory; and
- a processor, wherein the processor includes a substrate, including a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via comprises a plurality of substantially horizontal path layers including a single point of contact between substantially horizontal path layers, wherein the substantially horizontal path layers each contain only a portion of a geometric shape and that only in combination form a closed path around an axis.
13. The electronic appliance of claim 12, wherein the path comprises at least one loop around the axis.
14. The electronic appliance of claim 12, wherein the path is polygonal in shape.
15. The electronic appliance of claim 12, wherein the path comprises one or more turns in a same layer.
16. A method comprising:
- forming a plated through-hole; and
- forming a micro-via coupled with the throughhole, wherein the micro-via comprises a plurality of substantially horizontal path layers including a single point of contact between substantially horizontal path layers, wherein the substantially horizontal path layers each contain only a portion of a geometric shape and that only in combination form a closed path around an axis.
17. The method of claim 16, wherein the path is substantially circular in shape.
18. The method of claim 16, wherein the path is substantially rectangular in shape.
19. The method of claim 16, wherein the path comprises one or more turns in a same layer.
