Method and Apparatus to Monitor Circuit Variation Effects on Electrically ...

1. One or more monitor banks each comprising:

a first set one time programmable memory circuits representing a second set of one time programmable memory circuits, the first set of one time programmable memory circuits being programmed at a separate time instance from the second set of one time programmable memory circuits in order to determine whether the second set of one time programmable memory circuits have or will program successfully.

2. The one or more monitor banks of claim 1 wherein the first set of one time programmable memory circuits further comprises:

a first particular one time programmable memory circuit configured to always be expected to blow when the first set of one time programmable memory circuits is programmed, and;

a second particular one time programmable memory circuit configured to never be expected to blow when the first set of one time programmable memory circuits is programmed.

3. The one or more monitor banks of claim 2 wherein the first set of one time programmable memory circuits further comprises:

at least a third particular one time programmable memory circuit configured to be more difficult to blow than the second particular one time programmable memory circuit and easier to blow than the first particular one time programmable memory circuit.

4. The one or more monitor banks of claim 2 wherein the first set of one time programmable memory circuits further comprises:

a plurality of sequentially varying one time programmable memory circuits wherein each successive individual one time programmable memory circuit is configured to be more difficult to blow relative to the previous one time programmable memory circuit in the sequence.

5. The one or more monitor banks of claim 2 wherein the first set of one time programmable memory circuits is a set of test eFuses, the second set of one time programmable memory circuits is a set of functional eFuses, the first particular one time programmable memory circuit is a first test eFuse circuit, the second particular one time programmable memory circuit is a second test eFuse circuit, and the third particular one time programmable memory circuit is a third eFuse circuit.

6. The one or more monitor banks of claim 5 wherein the set of test eFuses further comprises:

a plurality of sequentially varying test eFuse circuits wherein each successive individual eFuse circuit is configured to be more difficult to blow relative to the previous eFuse circuit in the sequence.

7. The one or more monitor banks of claim 6 wherein upon programming the first set of eFuse circuits results in a first group of zero or more unblown eFuse circuits and a second group of zero or more blown eFuse circuits.

8. The one or more monitor banks of claim 6 wherein at least one monitor bank is located in a kerf area of a semiconductor wafer.

9. The one or more monitor banks of claim 6 wherein at least one monitor bank is located on a packaged semiconductor chip and is blown prior to the time the packaged semiconductor chip is placed into commerce.

10. The one or more monitor banks of claim 6 wherein at least one monitor bank is located on a packaged semiconductor chip and is blown subsequent to a determination that the packaged semiconductor chip is defective.

11. The one or more monitor banks of claim 6 wherein the first eFuse circuit is configured such that the amount of current passing through a first eFuse link is expected to always cause the first eFuse link to blow, wherein the second eFuse circuit is configured such that the amount of current passing through a second eFuse link is expected to never cause the second eFuse link to blow, and wherein the plurality of sequentially varying eFuse circuits are configured such that the amount of current passing through each individual eFuse link contained in the plurality of eFuse circuits sequentially increases.

12. The one or more monitor banks of claim 11 wherein the current passing through each eFuse link is controlled by one or more transistors.

13. The one or more monitor banks of claim 12 wherein the increasing amount of current passing though each eFuse link is controlled by decreasing the channel lengths of the one or more transistors.

14. The one or more monitor banks of claim 12 wherein increasing amount of current passing though each eFuse link is controlled by increasing the gate widths of the one or more transistors.

15. A semiconductor chip comprising a bank of eFuse circuitry used to determine if functional eFuse programming will be or has been reliable, the bank of eFuse circuitry comprising:

a first eFuse configured to be expected to always blow when the bank is programmed;

a second eFuse configured to be expected to never blow when the bank is programmed;

eFuse blow circuitry connected to each eFuse, utilized to provide a current to each eFuse, and;

eFuse sense circuitry connected to each test eFuse, utilized to determine whether each eFuse is blown or unblown.

16. The semiconductor chip of claim 15 further comprising:

at least a third eFuse configured to be more difficult to blow than the first eFuse, but less difficult to blow than the second eFuse.

17. The semiconductor chip of claim 15 further comprising:

a plurality of sequentially varying eFuses wherein each successive individual eFuse is configured to be more difficult to blow.

18. The semiconductor chip of claim 17 wherein the first eFuse is configured so the amount of the current passing through a first eFuse link will always blow the first eFuse link, wherein the second eFuse is configured such that the amount of the current passing through a second eFuse link will never blow the second eFuse link, and wherein the plurality of sequentially varying eFuses are configured such that the amount of the current passing through each individual eFuse link sequentially increases.

19. The semiconductor chip of claim 18 wherein the current passing through each eFuse link is controlled by one or more transistors located in the eFuse blow circuitry, and where the increasing amount of current passing though each eFuse link is controlled by decreasing the channel length of the one or more transistors, or by increasing the gate width of the one or more transistors.

20. A method of determining whether functional eFuses contained on a semiconductor chip or a semiconductor wafer will be or have been programmed successfully, comprising the steps of:

programming a monitor bank of test eFuses, the monitor bank being located on the semiconductor chip or the semiconductor wafer, each test eFuse having a test eFuse link, and a differing configuration wherein the amount of current passing through each test eFuse link differs;

sensing whether the test eFuses in the monitor bank have blown;

arranging the output monitor bank programming data in a bit line pattern;

determining at least one acceptable bit line blow pattern that results in an anticipated blow output;

comparing the output monitor bank programming bit line blow pattern with the at least one acceptable bit line blow pattern; and

determining that the functional eFuses will not blow successfully if the patterns do not match, or that the functional eFuses will blow successfully if the patterns do match.

21. The method of claim 20 further comprising the steps of:

determining that the semiconductor chip or semiconductor wafer is acceptable if the functional eFuses will blow successfully, or that the semiconductor chip or semiconductor wafer is unacceptable if the functional eFuses will not blow successfully.

22. A method of adjusting the functional eFuse circuit parameters to ensure the functional eFuse circuit will program successfully comprising the steps of:

programming a monitor bank of test eFuse circuits sensing whether each test eFuse circuit has blown

arranging the output monitor bank programming data in a bit line pattern;

determining at least one bit line blow pattern that results in an anticipated blow output;

comparing the output monitor bank programming bit line blow pattern with the at least one acceptable bit line blow pattern, and if the patterns do not match;

determining how much to adjust the functional circuit parameters accounting for the effect of one or more eFuse degradation characteristics, and;

adjusting the function eFuse circuit parameters the ensure the functional eFuse circuit will program successfully.