Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.
|US3265876||Dec 24, 1962||Aug 9, 1966||PARALLEL DATA ACCUMULATOR FOR OPERATING IN|
|US4138731||Dec 9, 1977||Feb 6, 1979||Fujitsu Limited||High speed binary and binary coded decimal adder|
|US4172288||Jun 16, 1978||Oct 23, 1979||Motorola, Inc.||Binary or BCD adder with precorrected result|
|US4278095||Jun 5, 1979||Jul 14, 1981||Exercise monitor system and method|
|US4441159||Jul 7, 1981||Apr 3, 1984||International Computers Ltd.||Digital adder circuit for binary-coded numbers of radix other than a power of two|
|US4707799||Jan 28, 1985||Nov 17, 1987||Kabushiki Kaisha Toshiba||Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction|
|US5007010||Mar 25, 1986||Apr 9, 1991||Unisys Corp. (Formerly Burroughs Corp.)||Fast BCD/binary adder|
|US7546328||Sep 15, 2004||Jun 9, 2009||Wisconsin Alumni Research Foundation||Decimal floating-point adder|
|US7743084||Dec 16, 2004||Jun 22, 2010||Wisconsin Alumni Research Foundation||Processing unit having multioperand decimal addition|
1. An integrated circuit microprocessor comprising:
- means for providing a pair of 8-bit operands;
- a parallel binary adder having 8 stages receiving the corresponding order operand bits and corresponding order carry-in bits and providing corresponding order straight binary sum bits and corresponding order straight binary carry-out bits;
- means for selectively providing a decimal operation command signal;
- first gating means responsive to said command signal for selectively modifying the 4th and 8th order binary carry-out bits concurrently with the binary addition of the operands by the adder to provide a 4th and an 8th order decimal carry-out bits and for applying the OR-function of the 4th order binary and decimal carry-out bits to the 5th adder stage as a carry-in bit; and
- second gating means responsive to said command signal for modifying said binary sum bits to provide an 8-bit result corresponding selectively to the binary coded decimal sum or difference of the operands.
2. An integrated circuit microprocessor comprising:
- means for providing two 4-bit operands;
- a parallel, 4-bit, straight binary adder receiving the operands and providing the binary sum thereof and a 4th order straight binary carry-out bit;
- means for selectively providing a decimal operation command signal;
- first gating means connected to the binary adder and responsive to said command signal for modifying said 4th order binary carry-out bit to provide a 4th order decimal carry-out bit concurrently with the addition of the operands by the binary adder; and
- second gating means connected to the adder to receive the binary sum of the operands and responsive to said command signal for modifying selected bits of said binary sum to selectively provide the binary coded decimal sum or difference of said operands.
3. A device comprising:
- binary adding means having N (N= 2, 3 . . . ) successive order sections each having 4 successive order stages each receiving the corresponding order bits of a pair of binary coded decimal operands and a corresponding order carry-in bit and provided to the corresponding order straight binary sum bit and a corresponding order straight binary carry-out bit applied to the next higher order stage as a carry-in bit;
- N-1 first gating means each associated with the corresponding order section of the adding means and each including means for providing a decimal carry-out bit corresponding to the carry-out bit of a binary coded decimal sum of the operand bits applied to the associated order section of the adding means;
- means for applying a carry-in bit to each lowest order stage of each section of the adding means the OR-function of the binary carry-out bit from the next lower order section and the same order decimal carry-out bit;
- N second gating means each associated with a corresponding order section of the adding means but removed therefrom and each selectively modifying the binary sum bits therefrom to provide binary coded decimal sum or difference bits of corresponding order.
4. A device as in claim 3 wherein each first gating means includes means receiving the corresponding order operand bits and providing said decimal carry-out bit only when the binary sum thereof corresponds to at least the decimal number 9.
5. A device comprising:
- means for combining a pair of operands, each comprising a plurality of successive order bits representing a number in a selected first binary code, in accordance with an arithmetic operation in a second binary code, different from the first, to provide a plurality of corresponding order result bits representing the result number which would have been obtained if the operands had been in said second code, said combining means including means for providing a selected order carry-out bit for said operation in said second code;
- first gating means for combining the operands to provide a selected order carry-out bit corresponding to the carry-out bit which would have resulted from a corresponding operation in said first code on said operands; and
- second gating means for combining said second code result bits to provide corresponding order first code result bits representing in said first binary code the number which would have resulted from carrying out in the first code said arithmetic opeation.
6. A device as in claim 5 wherein the means for combining the operands to provide the second code result bits comprises a 4-bit binary adder adding operands which are in binary coded decimal form, and the second gating means comprises means for providing said result bits in binary coded decimal form.
7. A device as in claim 5 wherein the means for combining the operands to provide the second code result bits comprises means for adding binary coded operands to provide the sum which would have resulted had the operands been in straight binary code.
8. A device as in claim 7 wherein the first gating means comprises means for providing an N-th order (N=4, 8, 12, . . . ) carry-out bit corresponding to the OR-function of the N-th order straight binary carry-out bit and the N-th order binary coded decimal carry-out bit of the sum of the operands.