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A system and method for recovering from a power failure in a digital camera comprises a power manager for detecting and handling power failures, an interrupt handler for responsively incrementing a counter device, service routines which register to receive notification of the power failure, and a processor for evaluating the counter and providing notification of the power failure to the service routines which may then assist the digital camera to recover from the power failure.

Inventor: Eric C. Anderson
Original Assignee: Apple Computer, Inc.
Primary Examiner: Xuan M. Thai
Current U.S. Classification: 713/300; 348/E05.024; 348/E05.042
International Classification: G06F 130

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Citations

Cited PatentFiling dateIssue dateOriginal AssigneeTitle
US5283792Oct 19, 1990Feb 1, 1994Benchmarq Microelectronics, Inc.Power up/power down controller and power fail detector for processor
US5359728Apr 9, 1992Oct 25, 1994Hewlett-Packard CompanyData integrity assurance in a disk drive upon a power failure
US5386552Jul 18, 1994Jan 31, 1995Intel CorporationPreservation of a computer system processing state in a mass storage device
US5475428Sep 9, 1993Dec 12, 1995Eastman Kodak CompanyMethod for processing color image records subject to misregistration
US5475441Dec 10, 1992Dec 12, 1995Eastman Kodak CompanyElectronic camera with memory card interface to a computer
US5477264Mar 29, 1994Dec 19, 1995Eastman Kodak CompanyElectronic imaging system using a removable software-enhanced storage device
US5493335Jun 30, 1993Feb 20, 1996Eastman Kodak CompanySingle sensor color camera with user selectable image record size
US5560022Jul 19, 1994Sep 24, 1996Intel CorporationPower management coordinator system and interface
US5634000Jul 31, 1991May 27, 1997Ascom Autelca AGPower-fail return loop

Referenced by

Citing PatentFiling dateIssue dateOriginal AssigneeTitle
US6175927Oct 6, 1998Jan 16, 2001International Business Machine CorporationAlert mechanism for service interruption from power loss
US6536671Dec 5, 2000Mar 25, 2003International Business Machines CorporationAutomatic recovery of integrated circuit cards
US6753625Mar 28, 2002Jun 22, 2004International Business Machines CorporationMethod and apparatus for implementing programmable battery shut off
US7295051Jun 15, 2005Nov 13, 2007Cypress Semiconductor Corp.System and method for monitoring a power supply level
US7342611Dec 10, 2003Mar 11, 2008Hewlett-Packard Development Company, L.P.Method for rapid power-on to first picture in a digital camera
US7368960Jun 15, 2005May 6, 2008Cypress Semiconductor Corp.Circuit and method for monitoring the integrity of a power supply
US8102457Dec 15, 1998Jan 24, 2012FlashPoint Technology, Inc.Method and apparatus for correcting aspect ratio in a camera graphical user interface
US8127232Dec 21, 2007Feb 28, 2012FlashPoint Technology, Inc.Method and apparatus for editing heterogeneous media objects in a digital imaging device
US8174503May 17, 2008May 8, 2012David H. CainTouch-based authentication of a mobile device through user generated pattern creation

Claims

1. A system for managing power conditions in a digital camera device, comprising:

a processor coupled to said digital camera device for controlling said digital camera device; and
a power manager coupled to said processor, said power manager including registers for containing status information, interrupt information, and control information;
said power manager providing said status information, said interrupt information, and said control information to said processor for controlling said digital camera device.

2. The system of claim 1 wherein said conditions include a low power level condition to which said processor responsively performs a powerdown sequence and a powerup sequence to protect data including captured image data in said digital camera device.

3. The system of claim 1 wherein said power manager uses a sensor device to obtain said power state information from a power source coupled to said digital camera device.

4. The system of claim 1 wherein said power manager further comprises a control register for storing said control information, an interrupt register for storing said interrupt information, and a condition register for storing said status information.

5. The system of claim 1 wherein said control information indicates the contents of memory devices coupled to said digital camera device.

6. The system of claim 5 wherein said control information includes a RESUME bit and a MSAVE bit which said power manager uses to indicate shutdown states for said digital camera device.

7. The system of claim 1 wherein said power manager further comprises a state machine, a LCD generator and a bus interface.

8. The system of claim 1 wherein said processor generates selected interrupts to control said digital camera device in response to said interrupt information from said power manager.

9. A method for managing power conditions in a digital camera device, comprising the steps of:

controlling said digital camera device with a processor coupled to said digital camera device;
storing status information, interrupt information, and control information in a power manager coupled to said processor; and
providing said status information, said interrupt information, and said control information to said processor for controlling said digital camera device.

10. The method of claim 9 wherein said conditions include a low power level condition to which said processor responsively performs a powerdown sequence and a powerup sequence to protect data including captured image data in said digital camera device.

11. The method of claim 9 wherein said power manager uses a sensor device to obtain said power state information from a power source coupled to said digital camera device.

12. The method of claim 9 wherein said power manager further comprises a control register for storing said control information, an interrupt register for storing said interrupt information, and a condition register for storing said status information.

13. The method of claim 9 wherein said control information indicates the contents of memory devices coupled to said digital camera device.

14. The method of claim 13 wherein said control information includes a RESUME bit and a MSAVE bit which said power manager uses to indicate shutdown states for said digital camera device.

15. The method of claim 9 wherein said power manager further comprises a state machine, a LCD generator and a bus interface.

16. The method of claim 9 wherein said processor generates selected interrupts to control said digital camera device in response to said interrupt information from said power manager.

17. A computer-readable medium comprising program instructions for managing power conditions in a digital camera device by performing the steps of:

controlling said digital camera device with a processor coupled to said digital camera device;
storing status information, interrupt information, and control information in a power manager coupled to said processor; and
providing said status information, said interrupt information, and said control information to said processor for controlling said digital camera device.

18. A system for managing power conditions in a digital camera device, comprising:

means for controlling said digital camera device with a processor coupled to said digital camera device;
means for storing status information, interrupt information, and control information in a power manager coupled to said processor; and
means for providing said status information, said interrupt information, and said control information to said processor for controlling said digital camera device.

Drawings