An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at...http://www.google.com/patents/US20050036367?utm_source=gb-gplus-sharePatent US20050036367 - Distributed write data drivers for burst access memories
