A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read...http://www.google.com/patents/US20070035995?utm_source=gb-gplus-sharePatent US20070035995 - METHOD OF PROGRAMMING A FOUR-LEVEL FLASH MEMORY DEVICE AND A RELATED PAGE BUFFER
