A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and...http://www.google.com/patents/US7380181?utm_source=gb-gplus-sharePatent US7380181 - Test circuit and method for hierarchical core
