A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are...http://www.google.com/patents/US7106655?utm_source=gb-gplus-sharePatent US7106655 - Multi-phase clock signal generator and method having inherently unlimited frequency capability
