A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on...http://www.google.com/patents/US7430578?utm_source=gb-gplus-sharePatent US7430578 - Method and apparatus for performing multiply-add operations on packed byte data
