A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The...http://www.google.com/patents/US4868629?utm_source=gb-gplus-sharePatent US4868629 - Self-aligned split gate EPROM
