A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register...http://www.google.com/patents/US5652900?utm_source=gb-gplus-sharePatent US5652900 - Data processor having 2n bits width data bus for context switching function
