A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared...http://www.google.com/patents/US4661900?utm_source=gb-gplus-sharePatent US4661900 - Flexible chaining in vector processor with selective use of vector registers as operand and result registers
