A bit length corresponding to a delay time of required data is preset in a bit length setting circuit (15). A write timing signal from an external control circuit (6) is applied to a write address decoder (3) and a read timing signal generating circuit (2). Input data is written into memory cells in...http://www.google.com/patents/US4876670?utm_source=gb-gplus-sharePatent US4876670 - Variable delay circuit for delaying input data
