A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided...http://www.google.com/patents/US20030086295?utm_source=gb-gplus-sharePatent US20030086295 - Semiconductor device that enables simultaneous read and write/read operation
