A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner...http://www.google.com/patents/US6521485?utm_source=gb-gplus-sharePatent US6521485 - Method for manufacturing wafer level chip size package
