A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete....http://www.google.com/patents/US20060224864?utm_source=gb-gplus-sharePatent US20060224864 - System and method for handling multi-cycle non-pipelined instruction sequencing
