A process is disclosed for making a self-aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first...http://www.google.com/patents/US3958323?utm_source=gb-gplus-sharePatent US3958323 - Three mask self aligned IGFET fabrication process
