In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having the same frequency. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference...http://www.google.com/patents/US5317202?utm_source=gb-gplus-sharePatent US5317202 - Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
