In a pipelined instruction execution system including a microstore for storing sequences of microinstruction addresses associated with each macroinstruction, a nanostore for randomly storing unique microinstructions, and an execution unit for executing the microinstructions, a no-op/prefetch apparatus,...http://www.google.com/patents/US4701842?utm_source=gb-gplus-sharePatent US4701842 - Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
