A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER...http://www.google.com/patents/US5953512?utm_source=gb-gplus-sharePatent US5953512 - Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer
