A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include a latch for storing...http://www.google.com/patents/US6219763?utm_source=gb-gplus-sharePatent US6219763 - System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit
