A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit...http://www.google.com/patents/US5805877?utm_source=gb-gplus-sharePatent US5805877 - Data processor with branch target address cache and method of operation
