A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between...http://www.google.com/patents/US5991225?utm_source=gb-gplus-sharePatent US5991225 - Programmable memory address decode array with vertical transistors
