A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry...http://www.google.com/patents/US5488319?utm_source=gb-gplus-sharePatent US5488319 - Latch interface for self-reset logic
