In a processor executing instructions speculatively or out-of-order, an apparatus for tracking traps, exceptions, and interrupts within the processor. A table stores front-end and back-end traps associated with an instruction, and an instruction retirement module retires the instructions in order if...http://www.google.com/patents/US6052777?utm_source=gb-gplus-sharePatent US6052777 - Method for delivering precise traps and interrupts in an out-of-order processor
