A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within...http://www.google.com/patents/US4758747?utm_source=gb-gplus-sharePatent US4758747 - Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor
