An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments,...http://www.google.com/patents/US7138828?utm_source=gb-gplus-sharePatent US7138828 - FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
