A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in...http://www.google.com/patents/US20020073369?utm_source=gb-gplus-sharePatent US20020073369 - Method and apparatus for controlling and observing data in a logic block-based asic
