A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. The bit lines are isolated from one another...http://www.google.com/patents/US5994231?utm_source=gb-gplus-sharePatent US5994231 - Process for depositing a stratified dielectric structure for enhancing the planarity of semiconductor electronic devices
