A three layer artificial neural network having an N terminal input, a two cell hidden and a single cell output layer generates an output parity signal indicating whether an even or an odd number of binary bits are asserted at the N terminal input. The two hidden layer neural cells have activation...
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Citations|
| 4897811 | N-dimensional coulomb neural network which provides for cumulative learning of internal representations | Jan 30, 1990 | | 4912655 | Adjusting neural networks | Mar 27, 1990 | | 4914603 | Training neural networks | Apr 3, 1990 | | 4972187 | Numeric encoding method and apparatus for neural networks | Nov 20, 1990 | | 5050095 | Neural network auto-associative memory with two rules for varying the weights | Sep 17, 1991 | | 5058180 | Neural network apparatus and method for pattern recognition | Oct 15, 1991 | | 5134396 | Method and apparatus for encoding and decoding data utilizing data compression and neural networks | Jul 28, 1992 | | 5170463 | Neuro-computer | Dec 8, 1992 | | 5268684 | Apparatus for a neural network one-out-of-N encoder/decoder | Dec 7, 1993 | | 5287533 | Apparatus for changing individual weight value of corresponding synaptic connection for succeeding learning process when past weight values satisfying predetermined condition | Feb 15, 1994 | | 5293453 | Error control codeword generating system and method based on a neural network | Mar 8, 1994 |
Referenced by|
| 5574827 | Method of operating a neural network | Nov 12, 1996 | | 5720002 | Neural network and method of using same | Feb 17, 1998 | | 5781701 | Neural network and method of using same | Jul 14, 1998 | | 6094438 | Parity detection device and method in CDMA mobile communications system | Jul 25, 2000 |
ClaimsWhat is claimed is: 1. A parity detecting neural network operating on an N-bit input field for providing a binary output signal that indicates if an even or odd number bits in the N-bit input field have been asserted, the neural network comprising: - (a) a multiplicity of N input terminals, each terminal for accepting a distinct bit from the N-bit input field;
- (b) a hidden layer having a first neural cell and a second neural cell, each neural cell including:
- (i) a set of N equally weighted synapses, each synapse connected to a distinct input terminal for producing a set of weighted output signals,
- (ii) a synaptic summing network for accepting the set of weighted output signals and for forming an output signal with a level proportional to a count of asserted bits in the N-bit input field,
- (iii) a nonlinear activation network with an input connected to the synaptic summing network output signal for producing an output signal that is a sum of a first signal with a signal level proportional to the synaptic summing network output signal for producing an output signal and a second signal that alternates polarity, having a first polarity if the synaptic summing network output signal level is proportional to an odd count of asserted bits and having an opposite second polarity if the synaptic summing network output signal level is proportional to an even count of asserted bits, the second neural cell nonlinear activation network having a second signal that is of opposite polarity to that of the first neural cell nonlinear activation network second signal;
- (c) an output layer having a single neural cell with a first synaptic input and a second synaptic input respectively connected to the first neural cell output signal and the second neural cell output signal for producing a binary output signal with a first state indicating an even count of asserted bits in the N-bit input field and a second state indicating an odd count of asserted bits in the N-bit input field by forming a difference signal representative of a difference between the output signal of the hidden layer first and second neural cell output signal, the binary output signal state being representative of the difference signal polarity.
2. The parity detecting neural network of claim 1 wherein the nonlinear activation network produces an output signal that varies monotonically with respect to the synaptic summing network output signal level. 3. The parity detecting neural network of claim 1 wherein the second signal of the nonlinear activation network output signal of the hidden layer first and second neural cell are of a same form but of opposite polarity. 4. The parity detecting neural network of claim 3 wherein the output layer single neural cell produces the binary output signal by forming a difference signal that is proportional to the difference between the second signal of the nonlinear activation network output signal of the hidden layer first neural cell and second neural cell. 5. A parity detecting neural network operating on an N-bit input field for providing a binary output signal that indicates if an even or odd number bits in the N-bit input field have been asserted, the neural network comprising: - (a) a multiplicity of N input terminals, each terminal for accepting a distinct bit from the N-bit input field;
- (b) a hidden layer having a first neural cell and a second neural cell, each neural cell including,
- (i) a set of N equally weighted synapses, each synapse connected to a distinct input terminal for producing a set of weighted output signal,
- (ii) a synaptic summing network for accepting the set of weighted output signals and for forming an output signal with a level proportional to a count of asserted bits in the N-bit input field,
- (iii) a nonlinear activation network with an input connected to the synaptic summing network output signal having a monotonically rising transfer characteristic with oscillating variations having a period corresponding to changes in input signal level representing changes in the count of asserted bits in the N-bit input field of two bits for producing an output signal that is indicative of whether the count of asserted bits in the N-bit input field is odd or even, both the first and second neural cell transfer characteristics having oscillating variations of the same period but of opposite polarity;
- (c) an output layer having a single neural cell with a first synaptic input and a second synaptic input respectively connected to the first neural cell output-signal and the second neural cell output signal for producing a binary output signal with a first state indicating an even count of asserted bits in the N-bit input field and a second state indicating an odd count of asserted bits in the N-bit input field by forming a difference signal representative of a difference between the output signal of the hidden layer first and second neural cell output signal, the binary output signal state being representative of the difference signal polarity.
6. The parity detecting neural network of claim 5 wherein the second signal of the nonlinear activation network output signal of the hidden layer first and second neural cell are of a same form but of opposite polarity. 7. The parity detecting neural network of claim 6 wherein the output layer single neural cell produces the binary output signal by forming a difference signal that is proportional to the difference between the second signal of the nonlinear activation network output signal of the hidden layer first neural cell and second neural cell. 8. A parity detecting neural network operating on an N-bit input field for providing a binary output signal that indicates if an even or odd number bits in the N-bit input field have been asserted, the neural network comprising: - (a) a multiplicity of N input terminals, each terminal for accepting a distinct bit from the N-bit input field;
- (b) a hidden layer having a first neural cell and a second neural cell, the first neural cell including,
- (i) a set of N equally weighted synapses, each synapse connected to a distinct input terminal for producing a set of weighted output signal,
- (ii) a synaptic summing network for accepting the set of weighted output signals and for forming an output signal with a level proportional to a count of asserted bits in the N-bit input field,
- (iii) a nonlinear activation network with an input connected to the synaptic summing network output signal for producing an output signal that is a sum of a first signal with a signal level proportional to the synaptic summing network output signal for producing an output signal that is a sum of a first signal with a signal level proportional to the synaptic summing network output signal and a second signal that alternates polarity, having a first polarity if the synaptic summing network output signal level is proportional to an even count of asserted bits and having an opposite second polarity if the synaptic summing network output signal level is proportional to an even count of asserted bits, the second neural cell including:
- (i) a set of N equally weighted synapses, each synapse connected to a distinct input terminal for producing a set of weighted output signal, and
- (ii) a synaptic summing network for accepting the set of weighted output signals and for forming an output signal with a level proportional to a count of asserted bits in the N-bit input field,
- (c) an output layer having a single neural cell with a first synaptic input and a second synaptic input respectively connected to the first neural cell output signal and the second neural cell output signal for producing a binary output signal with a first state indicating an even count of asserted bits in the N-bit input field and a second state indicating an odd count of asserted bits in the N-bit input field by forming a difference signal representative of a difference between the output signal of the hidden layer first and second neural cell output signal, the binary output signal states representative of the polarities of the difference signal.
9. The parity detecting neural network of claim 8 wherein the nonlinear activation network produces an output signal that varies monotonically with respect to the synaptic summing network output signal level. |
