The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC...http://www.google.com/patents/US20030005265?utm_source=gb-gplus-sharePatent US20030005265 - Checkpointing a superscalar, out-of-order processor for error recovery
