A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, is received. The macro instruction...http://www.google.com/patents/US20040083353?utm_source=gb-gplus-sharePatent US20040083353 - Staggering execution of a single packed data instruction using the same circuit
