An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the...http://www.google.com/patents/US6300188?utm_source=gb-gplus-sharePatent US6300188 - Fabrication process for reduced area storage node junction
