A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into...http://www.google.com/patents/US7251757?utm_source=gb-gplus-sharePatent US7251757 - Memory testing
