A clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are provided to a multiplexer...http://www.google.com/patents/US6744289?utm_source=gb-gplus-sharePatent US6744289 - Clock divider circuit with duty cycle correction and minimal additional delay
