A DRAM is constructed by a memory section, a multiplexer (MPX), an inverting circuit and a non-inverting circuit. The memory section stores data transferred through a data bus. The multiplexer selects a width of the data bus based on a mode signal for designating the bus width. The mode signal is shown...http://www.google.com/patents/US5630106?utm_source=gb-gplus-sharePatent US5630106 - DRAM controller including bus-width selection and data inversion
